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HD3-6408-9 Dataheets PDF



Part Number HD3-6408-9
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS Asynchronous Serial Manchester Adapter (ASMA)
Datasheet HD3-6408-9 DatasheetHD3-6408-9 Datasheet (PDF)

HD-6408 March 1997 CMOS Asynchronous Serial Manchester Adapter (ASMA) Description The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus. The Encoder converts serial NRZ data (typically from a shift register) to Manchester II encoded data, adding a sync pulse and parity bit. The Decoder recognizes this sync pulse and identifies it as a Command Sync or a Data Sync. The data is then decoded and shifted out in NRZ code (typically into a shif.

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HD-6408 March 1997 CMOS Asynchronous Serial Manchester Adapter (ASMA) Description The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus. The Encoder converts serial NRZ data (typically from a shift register) to Manchester II encoded data, adding a sync pulse and parity bit. The Decoder recognizes this sync pulse and identifies it as a Command Sync or a Data Sync. The data is then decoded and shifted out in NRZ code (typically into a shift register). Finally, the parity bit is checked. If there were no Manchester or parity errors the Decoder responds with a valid word signal. The Decoder puts the Manchester code to full use to provide clock recovery and excellent noise immunity at these very high speeds. The HD-6408 can be used in many commercial applications such as security systems, environmental control systems, serial data links and many others. It utilizes a single 12 x clock and achieves data rates of up to one million bits per second with a very minimum overhead of only 4 bits out of 20, leaving 16 bits for data. Features • Low Bit Error Rate • Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1MBit/s • Sync Identification and Lock-In • Clock Recovery • Manchester II Encoder, Decoder • Separate Encode and Decode • Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V • Single Power Supply • 24 Lead Package Ordering Information PACKAGE PDIP CERDIP TEMP. RANGE -40oC to +85oC -40oC to +85oC PART NUMBER HD3-6408-9 HD1-6408-9 PKG. NO. E24.6 E24.6 Pinout HD-6408 (DIP) TOP VIEW VW 1 ESC 2 TD 3 SDO 4 DC 5 BZI 6 BOI 7 UDI 8 DSC 9 CDS 10 DR 11 GND 12 24 VCC 23 EC 22 SCI 21 SD 20 SS 19 EE 18 SDI 17 BOO 16 OI 15 BZO 14 DBS 13 MR d CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2952.1 5-1 HD-6408 Block Diagrams ENCODER DECODER 11 23 EC ÷6 14 DBS 13 MR DR BIT COUNTER 1 VW SCI ESC SD 22 2 ÷2 BIT COUNTER TD 3 10 VALID WORD LATCH VALID WORD TEST CIRCUIT PARITY CHECK 21 RESET 20 SYNC CDS COUNT DECODER SYNC LATCH SS 5 DC CHARACTER FORMER 19 EE 15 16 17 BZO OI BOO 9 DSC 6 BZI BOI UDI 7 8 CLOCK SYNCHRONIZER CHARACTER IDENTIFIER NRZ OUTPUT PORT 4 SDO PARITY SDI 18 DATA TRANSITION FINDER 5-2 HD-6408 Pin Description PIN 1 2 TYPE O O SYMBOL VW ESC SECTION Decoder Encoder DESCRIPTION Output high indicates receipt of a VALID WORD. ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of ESC. TAKE DATA output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. SERIAL DATA OUT delivers received data in correct NRZ format. DECODER CLOCK input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the Decoder. Input a frequency equal to 12X the data rate. A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative state. This pin must be held high when the Unipolar input is used. A high input should be applied to BIPOLAR ONE IN when the bus is in its positive state, this pin must be held low when the Unipolar input is used. With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition finder circuit. If not used this input must be held low. DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ÷ 12), synchronized by the recovered serial data stream. COMMAND/DATA SYNC output high occurs during output of decoded data which was preceded by a Command synchronizing character. A low output indicates a Data synchronizing character. A high input to DECODER RESET during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. GROUND supply pin. A high on MASTER RESET clears the 2:1 counters in both the encoder and decoder and the ÷ 6 counter. DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER CLOCK. BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative sense of a bipolar line driver. A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states. BIPOLAR ONE OUT is an active low output designed to drive the one or positive sense of a bipolar line driver. SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preceding cycle being completed). SYNC SELECT actuates a Command sync for an input high and data sync for an input low. SEND DATA is an active high output which enables the external source of serial data. SEND CLOCK IN is 2X the Encoder data rate. ENCODER CLOCK is the input to the 6:1 divider. VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24) to GND (pin 12) is recommended. 3 O TD Decoder 4 5 O I SDO D.


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