Document
HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15530 is a high performance CMOS device intended to service the requirements of MlL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate completely independent of each other, except for the Master Reset functions. This circuit meets many of the requirements of MIL-STD1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. This integrated circuit is fully guaranteed to support the 1MHz data rate of MlL-STD-1553 over both temperature and voltage. It interfaces with CMOS, TTL or N channel support circuitry, and uses a standard 5V supply. The HD-15530 can also be used in many party line digital data communications applications, such as an environmental control system driven from a single twisted pair cable of fiber optic cable throughout the building.
Features
• Support of MlL-STD-1553 • Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s • Sync Identification and Lock-In • Clock Recovery • Manchester II Encode, Decode • Separate Encode and Decode • Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE CERDIP TEMP. RANGE -40oC to +85oC -55oC to +125oC SMD# CLCC -40oC to +85oC -55oC to +125oC -40oC to +85oC 1.25 MEGABIT/s HD1-15530-9 HD1-15530-8 7802901JA HD4-15530-9 HD4-15530-8 78029013A HD3-15530-9 E24.6 J28.A PKG. NO. F24.6
SMD# PDIP
Pinouts
HD-15530 (CERDIP, PDIP) TOP VIEW
VALID WORD 1 ENCODER SHIFT CLK 2 TAKE DATA 3 SERIAL DATA OUT 4 DECODER CLK 5 BIPOLAR ZERO IN 6 BIPOLAR ONE IN 7 UNIPOLAR DATA IN 8 DECODER SHIFT CLK 9 COMMAND/ DATA SYNC 10 DECODER RESET 11 GND 12 24 VCC 23 ENCODER CLK 22 SEND CLK IN 21 SEND DATA 20 SYNC SELECT 19 ENCODER ENABLE 18 SERIAL DATA IN 17 BIPOLAR ONE OUT 16 OUTPUT INHIBIT BIPOLAR 15 ZERO OUT 14 ÷ 6 OUT 13 MASTER RESET NC BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK 7 8 9 10 11 12 COMMAND/ DATA SYNC 13 DECODER RESET 14 GND 15 MASTER RESET 16 17 BIPOLAR ZERO OUT 18 OUTPUT INHIBIT 23 22 21 20 19 NC SYNC SELECT ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT DECODER CLK NC 5 6 SERIAL DATA OUT
HD-15530 (CLCC) TOP VIEW
TAKE DATA ENCODER SHIFT CLK ENCODER CLK SEND CLK IN 27 26 25 24 SEND DATA NC
VALID WORD 1
4
3
2
÷ 6 OUT
VCC 28
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2960.1
5-142
HD-15530 Block Diagrams
ENCODER
12 13 22 14 GND MASTER RESET SEND CLK IN VCC OUTPUT INHIBIT 24 UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN 8 7 6 TRANSITION FINDER CHARACTER IDENTIFIER
DECODER
3 TAKE DATA 10 4 5 BIT RATE CLK COMMAND.