Receiver. DTC34LF86L Datasheet

DTC34LF86L Receiver. Datasheet pdf. Equivalent


Part Number

DTC34LF86L

Description

+3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver

Manufacture

DOESTEK

Total Page 7 Pages
Datasheet
Download DTC34LF86L Datasheet


DTC34LF86L
DTC34LF8 6L/DTC34LR86L
LVDS Product
DTC34LF86L/DTC34LR86L (Rev. 2.2)
REVISED APR. 2009
+3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver - 85MHz
General Description
The D TC34LF86L/LR86L rec eivers co nvert the L VDS
(Low Voltage Differential Signaling) data streams back
into 28 bit s of CMOS/ TTL dat a with falling edge
(DTC34LF86L) or risin g edge (DTC34LR86L) clock for
convenient int erface with a variet y of L CD p anel
controllers.
A phase-locked transmit clock is transmitte d in p arallel
with the data streams ove r a fif th L VDS link. A
transmitter (DTC34LM85L) w ill inter-o perate w ith a
Falling/Rising edg e rec eiver (DT C34LF86L/LR86L)
without any translation logic.
Using a 8 5 MHz clock, the dat a throu ghputs is 297.5
Mbytes/sec. This chip set is an ide al mean s to solve
EMI and ca ble size problems associat ed with wide,
high speed TTL interfaces.
Features
Wide frequency range : 20 to 85 MHz shift
clock support
Narrow bus (10 lines) reduces cable size
Sing le 3.3V supply
Po wer-Down Mode
Single pixel per clock XGA (1024x768) ready
Supports VGA, SVGA, XGA and SXGA
Up to 297.5 Megabytes/sec bandwidth
Up to 2.38 Gbps throughput
300mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 56-lead TSSOP package (PB Free)
Comp atible with TIA/EIA-644 LVDS standard
Compatible with the National DS90C386,
T hine THC63LVDF84A
Block Diagram
DTC34LF86L/DTC34LR86L
CMOS/TTL OUTPUTS
8
RED
LVDS DATA
( 140 TO 595Mbit/s
On Each LVDS
Channel )
8
GRN
8
BLU
HSYNC
VSYNC
DE(Data Enable)
CNTL
RCLK+/-
(20MHz ~ 85MHz)
PLL CLKOUT
(20MHz ~ 85MHz)
/PDN(Power Down)
-1-
DOESTEK Co., Ltd.
http://www.Datasheet4U.com

DTC34LF86L
DTC34LF8 6L/DTC34LR86L
Electrical Characteristics
Vcc=3.0 ~ 3.6V @ Ta=-10 ~ +70°C
CMOS/TTL DC SPECIFICATIONS
Symbol Pa
rameter
VIH High Level Input Voltage
VIL Low Level Input Voltage
VOH High Level Output Voltage
VOL Low Level Output Voltage
IIN Inpu
t Current
IOS Output Short Circuit Current
Conditions
IOH = -4mA
IOL = 4mA
0V VIN Vcc
VOUT = 0V
Min Typ Max Units
2.0 Vcc V
GND
0.8 V
2.4 V
0.4 V
±10 uA
-50 mA
LVDS RECEIVER DC SPECIFICATIONS
Symbol Pa
rameter
Conditions
Min Typ Max Units
Differential Input
VTH
High Threshold
Differential Input
VTL
Low Threshold
VOC = +1.2V
-100
+100
mV
mV
IIN Inpu
t Current
VIN = +2.4V/0V, Vcc = 3.6V
±10 uA
RECEIVER SUPPLY CURRENT
Symbol Pa
rameter
ICCRG
Receiver Supply Current
(16 Grayscale)
ICCRW
Receiver Supply Current
(Worst Case)
ICCRP
Receiver Supply Current
(Power Down)
Conditions
CL = 8pF, f = 85MHz, Vcc = 3.3V
16 Grayscale Pattern
CL = 8pF, f = 85MHz, Vcc = 3.3V
Worst Case Pattern
/PDN=0V 10
Typ Max Units
60 mA
95 mA
uA
Absolute Maximum Ratings (Note1)
Supply Voltage (Vcc)
-0.3 to +4.0V
CMOS/TTL Input Voltage -0.3V to (Vcc + 0.3V)
CMOS/TTL Output Voltage -0.3V to (Vcc + 0.3V)
LVDS Driver Output Voltage -0.3V to (Vcc + 0.3V)
Output Short Circuit Duration Continuous
Junction Temperature +150°C
Storage Temperature Range –65°C to 150°C
Lead Temperature (Soldering, 4 sec.) +260°C
Maximum Power Dissipation @ 25°C 1.4W
(Note 1)
"Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be gu aranteed. They are not mean t
to imply that the device should be operat ed at these limits. The
tables of "Electrical Characteristics" specify conditions for device
operation
- 2 - DOESTEK Co., Ltd.


Features DTC34LF8 6L/DTC34LR86L LVDS Product DTC 34LF86L/DTC34LR86L (Rev. 2.2) +3.3V LVD S 24Bit Flat Panel Display (FPD) Receiv er - 85MHz General Description The D TC 34LF86L/LR86L rec eivers co nvert the L VDS (Low Voltage Differential Signalin g) data streams back into 28 bit s of C MOS/ TTL dat a with falling edge (DTC34 LF86L) or risin g edge (DTC34LR86L) clo ck for convenient int erface with a var iet y of L CD p anel controllers. A pha se-locked transmit clock is transmitte d in p arallel with the data streams ov e r a fif th L VDS link. A a transmitte r (DTC34LM85L) w ill inter-o perate w i th without any translation logic. Using a 8 5 MHz clock, the dat a throu ghput s is 297.5 Mbytes/sec. This chip set is an ide al mean s to solve EMI and ca b le size problems associat ed with wide, high speed TTL interfaces. ▓ REVISE D APR. 2009 Features ▓ Wide frequen cy range : 20 to 85 MHz shift clock sup port Narrow bus (10 lines) reduces cabl e size ▓ Sing le 3.3V supply ▓ Po wer-Down Mode ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ S.
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