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HD44H11 Dataheets PDF



Part Number HD44H11
Manufacturers Hi-Sincerity Mocroelectronics
Logo Hi-Sincerity Mocroelectronics
Description NPN EPITAXIAL PLANAR TRANSISTOR
Datasheet HD44H11 DatasheetHD44H11 Datasheet (PDF)

HD61830/HD61830B LCDC (LCD Timing Controller) ADE-207-275(Z) '99.9 Rev. 0.0 Description The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal driving signals. It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on liquid crystal display and a character mode in which characters are displayed by st.

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HD61830/HD61830B LCDC (LCD Timing Controller) ADE-207-275(Z) '99.9 Rev. 0.0 Description The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal driving signals. It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on liquid crystal display and a character mode in which characters are displayed by storing character codes in the external RAM and developing them into the dot patterns with the internal character generator ROM. Both modes can be provided for various applications. The HD61830/HD61830B is produced by the CMOS process. Thus, combined with a CMOS microcontroller it can complete a liquid crystal display device with lower power dissipation. Features • Dot matrix liquid crystal graphic display controller • Display control capacity  Graphic mode: 512k dots (216 bytes)  Character mode: 4096 characters (212 characters) • Internal character generator ROM: 7360 bits  160 types of 5 × 7 dot characters  32 types of 5 × 11 dot characters Total 192 characters  Can be extended to 256 characters (4 kbytes max.) with external ROM 1 HD61830/HD61830B • Interfaces to 8-bit MPU • Display duty cycle (can be selected by a program) Static to 1/128 duty cycle • Various instruction functions  Scroll, cursor on/off/blink, character blink, bit manipulation • Display method: Selectable A or B types • Internal oscillator (with external resistor and capacitor) HD61830 • Operating frequency  1.1 MHz HD61830  2.4 MHz HD61830B • Low power dissipation • Power supply: Single +5 V ±10% • CMOS process 2 HD61830/HD61830B Differences between Products HD61830 and HD61830B HD61830 Oscillator Operating frequency Pin arrangement and signal name Package marking to see figure Internal or external 1.1 MHz Pin 6: C Pin 7: R Pin 9: CPO A HD61830B External only 2.4 MHz Pin 6: CE Pin 7: OE Pin 9: NC B Package Marking 3D13 A HD61830A00 JAPAN Lot No. 3D13 B HD61830B00 JAPAN Lot No. Ordering Information Type No. HD61830A00H HD61830B00H Package 60-pin plastic QFP (FP-60) 3 HD61830/HD61830B Pin Arrangement MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 56 MA9 55 54 53 52 51 50 49 48 47 FP-60 (Top view) 46 45 44 43 42 41 40 39 38 37 24 25 26 27 28 29 30 31 32 33 34 35 36 MB 5 4 3 2 1 60 59 58 57 MA10 MA11 MA12 MA13 MA14 MA15 D2 D1 CL2 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 MD0 MD1 (CE) C (OE) R CR (NC) CPO FLM CL1 SYNC WE RES CS E R/W RS MA GND DB7 DB6 DB5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MD7 MD6 MD5 MD4 MD3 DB4 DB3 DB2 DB1 DB0 ( ) is for HD61830B 4 MD2 VCC HD61830/HD61830B Terminal Functions Symbol DB0–DB7 CS R/W RS E CR C R CPO CE OE Pin Number 28–21 15 17 18 16 8 6 7 9 6 7 I/O I/O I I I I I — — O O O Function Data bus: Three-state I/O common terminal Data is transferred to MPU through DB0 to DB7. Chip select: Selected state with CS = 0 Read/Write:R/W = 1: MPU ← HD61830 R/W = 0: MPU → HD61830 Register select: RS = 1: Instruction register RS = 0: Data register Enable: Data is written at the fall of E Data can be read while E is 1 CR oscillator (HD61830), External clock input (HD61830B) CR oscillator to capacitor (HD61830 only) CR oscillator to resistor (HD61830 only) Clock signal for HD61830 in slave mode (HD61830 only) Chip enable (HD61830B only) CE = 0: Chip enables make external RAM in active Output enable (HD61830B only) OE = 1: Output enable informs external RAM that HD61830B requires data bus NC MA0–MA15 9 4–1, 60–49 Open Unused terminal. Don’t connect any wires to this terminal (HD61830B only) O External RAM address output In character mode, the line code for external CG is output through MA12 to MA15 (0: Character 1st line, F: Character 16th line) Display data bus: Three-state I/O common terminal ROM data input: Dot data from external character generator is input Write enable: Write signal for external RAM Display data shift clock for LCD drivers Display data latch signal for LCD drivers Frame signal for display synchronization Signal for converting liquid crystal driving signal into AC, A type Signal for converting liquid crystal driving signal into AC, B type Display data serial output D1: For upper half of screen D2: For lower half of screen Synchronous signal for parallel operation Three-state I/O common terminal (with pull-up MOS) Master: Synchronous signal is output Slave: Synchronous signal is input Reset: Reset = 0 results in display off, slave mode and Hp = 6 MD0–MD7 RD0–RD7 WE CL2 CL1 FLM MA MB D1 D2 SYNC 37–30 45–38 13 46 11 10 19 5 47 48 12 I/O I O O O O O O O I/O RES 14 I 5 Multiplexer I/O interface circuit 6 SYNC CL1 MA MB FLM (CE) (OE) WE Dot counter (DC) RAM * MD0–MD7 Dot registers (DR) 8 4 Character generator ROM (CGROM) 8 6 8 Cursor signal generator Control signal Line address counter Refesh address 16 counter (1) (RAC1) Refesh address 16 counter (2) (RAC2) Cursor addres.


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