DatasheetsPDF.com

SGN02G72F1BQ1SA-CCRT

Swissbit

204 Pin ECC SO-DIMM

Data Sheet Rev.1.0 16.09.2013 2048MB DDR3 – SDRAM ECC SO-UDIMM 204 Pin ECC SO-DIMM SGN02G72F1BQ1SA-xx[E/W]RT 2GByte i...


Swissbit

SGN02G72F1BQ1SA-CCRT

File Download Download SGN02G72F1BQ1SA-CCRT Datasheet


Description
Data Sheet Rev.1.0 16.09.2013 2048MB DDR3 – SDRAM ECC SO-UDIMM 204 Pin ECC SO-DIMM SGN02G72F1BQ1SA-xx[E/W]RT 2GByte in FBGA Technology RoHS compliant Features:       204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double Data Rate synchronous DRAM Module Module organization: single rank 256M x 72 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V 1.5V I/O ( SSTL_15 compatible) Fly-by-bus with termination for C/A & CLK bus 2 On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM Gold-contact pad This module is fully pin and functional compatible to the JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design spec. and JEDEC- Standard MO-268. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR3 - SDRAM component Samsung K4B2G0846Q-BYK0 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package 8-bit prefetch architecture Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type. On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh, Self Refresh and Power Down Modes. ZQ Calibration for output driver and ODT. System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Options:  Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1600 MT/s CL11 Module density 2GByte with 9 dies and 1 rank Standard Grade Grade E Grade W (TA) (TC) (TA) (TC) (TA) (TC) 0°C to...




Similar Datasheet




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)