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D Flip-Flop. MC54HC74A Datasheet

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D Flip-Flop. MC54HC74A Datasheet






MC54HC74A Flip-Flop. Datasheet pdf. Equivalent




MC54HC74A Flip-Flop. Datasheet pdf. Equivalent





Part

MC54HC74A

Description

Dual D Flip-Flop



Feature


MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D Flip-Flop with Set and Reset Hig h–Performance Silicon–Gate CMOS The MC54/74HC74A is identical in pinout to the LS74. The device inputs are compat ible with standard CMOS outputs; with p ullup resistors, they are compatible wi th LSTTL outputs. This device consists of two D flip–flops with individual S et, Reset, and Clock inp.
Manufacture

Motorola

Datasheet
Download MC54HC74A Datasheet


Motorola MC54HC74A

MC54HC74A; uts. Information at a D–input is trans ferred to the corresponding Q output on the next positive going edge of the cl ock input. Both Q and Q outputs are ava ilable from each flip–flop. The Set a nd Reset inputs are asynchronous. • • • • • Output Drive Capabil ity: 10 LSTTL Loads Outputs Directly In terface to CMOS, NMOS, and TTL Operatin g Voltage Range: 2.0 to 6.0 V Low .


Motorola MC54HC74A

Input Current: 1.0 µA High Noise Immuni ty Characteristic of CMOS Devices In Co mpliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Compl exity: 128 FETs or 32 Equivalent Gates MC54/74HC74A J SUFFIX CERAMIC PACKAGE CASE 632–08 1 14 14 1 N SUFFIX PLA STIC PACKAGE CASE 646–06 14 1 D SUF FIX SOIC PACKAGE CASE 751A–03 DT SUFF IX TSSOP PACKAGE CASE 948G–.


Motorola MC54HC74A

01 14 1 ORDERING INFORMATION MC54HCXXA J MC74HCXXAN MC74HCXXAD MC74HCXXADT Cer amic Plastic SOIC TSSOP LOGIC DIAGRAM PIN ASSIGNMENT RESET 1 DATA 1 1 RESET 1 2 5 Q1 DATA 1 CLOCK 1 CLOCK 1 SET 1 RE SET 2 DATA 2 3 4 13 GND 12 9 Q2 7 8 Q2 6 Q1 SET 1 Q1 Q1 1 2 3 4 5 6 14 13 12 1 1 10 9 VCC RESET 2 DATA 2 CLOCK 2 SET 2 Q2 CLOCK 2 SET 2 11 10 PIN 14 = VCC PIN 7 = GND 8 Q2 .

Part

MC54HC74A

Description

Dual D Flip-Flop



Feature


MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D Flip-Flop with Set and Reset Hig h–Performance Silicon–Gate CMOS The MC54/74HC74A is identical in pinout to the LS74. The device inputs are compat ible with standard CMOS outputs; with p ullup resistors, they are compatible wi th LSTTL outputs. This device consists of two D flip–flops with individual S et, Reset, and Clock inp.
Manufacture

Motorola

Datasheet
Download MC54HC74A Datasheet




 MC54HC74A
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D Flip-Flop with Set
and Reset
High–Performance Silicon–Gate CMOS
The MC54/74HC74A is identical in pinout to the LS74. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two D flip–flops with individual Set, Reset, and
Clock inputs. Information at a D–input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip–flop. The Set and Reset inputs are
asynchronous.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAM
RESET 1
DATA 1
1
2
5
Q1
3
CLOCK 1
SET 1
RESET 2
4
13
DATA 2 12
6
Q1
9
Q2
11
CLOCK 2
8
Q2
10
SET 2
PIN 14 = VCC
PIN 7 = GND
MC54/74HC74A
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
RESET 1
DATA 1
CLOCK 1
SET 1
Q1
Q1
GND
1
2
3
4
5
6
7
14 VCC
13 RESET 2
12 DATA 2
11 CLOCK 2
10 SET 2
9 Q2
8 Q2
FUNCTION TABLE
Inputs
Set Reset Clock Data
LH
HL
LL
HH
HH
HH
HH
HH
XX
XX
XX
H
L
LX
HX
X
Outputs
QQ
HL
LH
H* H*
HL
LH
No Change
No Change
No Change
* Both outputs will remain high as long as
Set and Reset are low, but the output
states are unpredictable if Set and Reset
go high simultaneously.
10/95
© Motorola, Inc. 1995
3–1 REV 6




 MC54HC74A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC74A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
DC Output Current, per Pin
± 25
DC Supply Current, VCC and GND Pins
± 50
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
750
500
450
V
V
mA
mA
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Plastic DIP, SOIC or TSSOP Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFor high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
2.0 6.0
0 VCC
– 55 + 125
V
V
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figures 1, 2, 3)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
Parameter
Minimum High–Level Input
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL MaximumLow–LevelInput
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
Maximum Low–Level Output
Voltage
Test Conditions
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 4.0 mA
v|Iout| 5.2 mA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 4.0 mA
v|Iout| 5.2 mA
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
1.5 1.5 1.5
3.15 3.15 3.15
4.2 4.2 4.2
0.5 0.5 0,5
1.35 1.35 1.35
1.8 1.8 1.8
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
3.98 3.84
5.48 5.34
3.7
5.2
0.1 0.1 0.1
0.1 0.1 0.1
0.1 0.1 0.1
0.26 0.33
0.26 0.33
0.4
0.4
Unit
V
V
V
V
MOTOROLA
3–2 High–Speed CMOS Logic Data
DL129 — Rev 6




 MC54HC74A
MC54/74HC74A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) – continued
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
Iin Maximum Input Leakage Current Vin = VCC or GND
6.0 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC MaximumQuiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 2.0 20 80 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfmax
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
VCC
V
2.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
6.0 4.8 4.0
30 24 20
35 28 24
Unit
MHz
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0 100 125 150 ns
4.5 20 25 30
6.0 17 21 26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0 105 130 160 ns
4.5 21 26 32
6.0 18 22 27
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0 75
4.5 15
6.0 13
95 110 ns
19 22
16 19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin Maximum Input Capacitance
— 10 10 10 pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
39 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTIMING REQUIREMENTS (Inputtr=tf=6.0ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtsu
Parameter
Minimum Setup Time, Data to Clock
(Figure 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎth MinimumHoldTime,ClocktoData
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtrec Minimum Recovery Time, Set or Reset Inactive to Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw MinimumPulseWidth,Clock
(Figure 1)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw MinimumPulseWidth,SetorReset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figures 1, 2, 3)
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
80 100 120
16 20 24
14 17 20
3.0 3.0 3.0
3.0 3.0 3.0
3.0 3.0 3.0
8.0 8.0 8.0
8.0 8.0 8.0
8.0 8.0 8.0
60 75 90
12 15 18
10 13 15
60 75 90
12 15 18
10 13 15
1000
500
400
1000
500
400
1000
500
400
Unit
ns
ns
ns
ns
ns
ns
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA



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