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HD74AC174 Dataheets PDF



Part Number HD74AC174
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description Hex D-Type Flip-Flop with Master Reset
Datasheet HD74AC174 DatasheetHD74AC174 Datasheet (PDF)

HD74AC174 Hex D-Type Flip-Flop with Master Reset Description The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Feature • Outputs Source/Sink 24 mA Pin Arrangement MR 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 (Top view) 16 VCC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q.

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HD74AC174 Hex D-Type Flip-Flop with Master Reset Description The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Feature • Outputs Source/Sink 24 mA Pin Arrangement MR 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 (Top view) 16 VCC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP HD74AC174 Logic Symbol D0 D1 D2 CP MR D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 Pin Names D0 to D5 CP MR Q0 to Q5 Data Inputs Clock Pulse Input Master Reset Input Outputs Functional Description The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR ) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the Master Reset (MR ) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs MR L H H H H : L : X : : L High Voltage Level Low Voltage Level Immaterial Low-to-High Transition of Clock CP X D X H L X Output Q L H L Q 2 HD74AC174 Logic Diagram MR CP D5 D4 D3 D2 D1 D0 D Q D Q D Q D Q D Q D Q CP CD CP CD CP CD CP CD CP CD CP CD Q5 Q4 Q3 Q2 Q1 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Symbol I CC I CC Max 80 8.0 Unit µA µA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C AC Characteristics: HD74AC174 Ta = +25°C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Qn Propagation delay CP to Qn Propagation delay MR to Q n Note: t PHL t PHL t PLH Symbol f max VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min 90 100 1.0 1.0 1.0 1.0 1.0 1.0 Typ 100 125 9.0 6.0 8.5 6.0 9.0 7.0 Max — — 11.5 8.5 11.0 8.0 11.5 9.0 Ta = –40°C to +85°C CL = 50 pF Min 70 100 1.0 1.0 1.0 1.0 1.0 1.0 Max — — 12.5 9.5 12.0 9.0 12.5 10.5 ns ns ns Unit MHz 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 3 HD74AC174 AC Operating Requirements: HD74AC174 Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Dn to CP Hold time, HIGH or LOW Dn to CP MR pulse width, LOW tw th Symbol t su VCC (V)*1 Typ 3.3 5.0 3.3 5.0 3.3 5.0 CP pulse width tw 3.3 5.0 Recovery time MR to CP Note: t rec 3.3 5.0 2.5 2.0 1.0 0.5 1.0 1.0 1.0 1.0 0 0 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 6.5 5.0 3.0 3.0 5.5 5.0 5.5 5.0 2.5 2.0 7.0 5.5 3.0 3.0 7.0 5.0 7.0 5.0 2.5 2.0 ns ns ns ns Unit ns 1. Voltage Range 3.3 is 3.3 .


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