HD74ACT112

HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features Outputs Source/Sink 24 mA HD74ACT112 has TTL-Compatible Inputs Pin Arrangement CP1 1 K1 2 J1 3 SD1 4 Q1 5 Q1 6 Q2 7 GND 8 (Top view) 16 VCC 15 CD1 14 CD2 13 CP2 12 K2 11 J2 10 SD2 9 Q2 HD74AC112/HD74ACT112 Logic Symbol 4 SD1 J1 CP1 K1 Q1 Q1 5 10 SD2 J2 CP2 K2 Q2 7 Q2 9 3 1 2 11 13 6 12 CD1 15 CD2 14 VCC = Pin16 GND = Pin8 Pin Names J1, J2, K1, K2 CP1, CP2 C D1, CD2 S D1, SD2 Q1, Q2, Q1, Q 2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active Low) Direct Set Inputs (Active Low) Outputs Asynchronous Inputs: Low input to SD sets Q to High level Low input to CD sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High 2 HD74AC112/HD74ACT112 Truth Table Inputs @tn J L L H H tn tn + 1 H L : : : : K L H L H Bit time before clock pulse. Bit time after clock pulse. High Voltage Level Low Voltage Level Outputs @tn + 1 Q Qn L H Qn Logic Diagram SD CD J K...