Document
HD74AC138/HD74ACT138
1-of-8 Decoder/Demultiplexer
Description
The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a 1-of-32 decoder using four HD74AC138/HD74ACT138 devices and one inverter.
Features
• • • • • Demultiplexing Capability Multiple Input Enable for Easy Expansion Active LOW Mutually Exclusive Outputs Outputs Source/Sink 24 mA HD74ACT138 has TTL-Compatible Inputs
HD74AC138/HD74ACT138
Pin Arrangement
A0 1 A1 2 A2 3 E1 4 E2 5 E3 6 O7 7 GND 8 (Top view)
16 VCC 15 O0 14 O1 13 O2 12 O3 11 O4 10 O5 9 O6
Logic Symbol
A0 A1 A2
E1
E2 E3
O0 O1 O2 O3 O4 O5 O6 O7
Pin Names
A0 to A2 E1 to E 2 E3 O0 to O 7 Address Inputs Enable Inputs Enable Input Outputs
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HD74AC138/HD74ACT138
Functional Description
The HD74AC138/HD74ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0 to O7). The HD74AC138/HD74ACT138 features three Enable inputs, two active-Low (E1, E2) and one active-High (E3). All outputs will be High unless E1 and E2 are Low and E 3 is High. This multiple enabled function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four HD74AC138/HD74ACT138 devices and one inverter (See Figure a). The HD74AC138/HD74ACT138 can be used as an 8-output demultiplexer by using one of the active Low Enable inputs as the data input and the other Enable inputs as strobes. The Enables inputs which are not used must be permanently tied to their appropriate active-High or active-Low state.
Truth Table
Inputs E1 H X X L L L L L L L L H : L : X : E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H Outputs O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L
High Voltage Level Low Voltage Level Immaterial
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HD74AC138/HD74ACT138
Logic Diagram
A2 A1 A0 E1 E2 E3
O7
O6
O5
O4
O3
O2
O1
O0
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure a: Expansion of 1-of-32 Decoding
A0 A1 A2
’04
A3 A4 H 123 A0 A1 A2 E A0 A1 A2 123 E A0 A1 A2 123 E A0 A1 A2 123 E
O0 O1 O2 O3 O4 O5 O6 O7 O0
O0 O1 O2 O3 O4 O5 O6 O7
O0 O1 O2 O3 O4 O5 O6 O7
O0 O1 O2 O3 O4 O5 O6 O7 O31
4
HD74AC138/HD74ACT138
DC Characteristics (unless otherwise specified)
Item Maximum quiescent supply current Maximum quiescent supply current Maximum ICC/input (HD74ACT138) Symbol I CC I CC I CCT Max 80 8.0 1.5 Unit µA µA mA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C VIN = VCC – 2.1 V, VCC = 5.5 V Ta = Worst case
AC Characteristics: HD74AC138
Ta = +25°C CL = 50 pF Item Propagation delay An to On Propagation delay An to On Propagation delay E1 or E 2 to On Propagation delay E1 or E 2 to On Propagation delay E3 to On Propagation delay E3 to On Note: t PHL t PLH t PHL t PLH t PHL Symbol t PLH VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ 8.5 6.5 8.0 6.0 11.0 8.0 9.5 7.0 11.0 8.0 8.5 6.0 Max 13.0 9.5 12.5 9.0 15.0 11.0 13.5 9.5 15.5 11.0 13.0 8.0 Ta = –40°C to +85°C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 15.0 10.5 14.0 10.5 16.0 12.0 15.0 10.5 16.5 12.5 14.0 9.5 ns ns ns ns ns Unit ns
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HD74AC138/HD74ACT138
AC Characteristics: HD74ACT138
Ta = +25°C CL = 50 pF Item Propagation delay An to On Propagation delay An to On Propagation delay E1 or E 2 to On Propagation delay E1 or E 2 to On Propagation delay E3 to On Propagation delay E3 to On Note: Symbol t PLH t PHL t PLH t PHL t PLH t PHL VCC (V)*1 5.0 5.0 5.0 5.0 5.0 5.0 Min 1.0 1.0 1.0 1.0 1.0 1.0 Typ 7.0 6.5 8.0 7.5 8.0 6.5 Max 10.5 10.5 11.5 11.5 12.0 10.5 Ta = –40°C to +85°C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 11.5 11.5 12.5 12.5 13.0 11.5 Unit ns ns ns ns ns ns
1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD Typ 4.5 60.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V
6
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hitachi Code JEDEC EIAJ Weight (reference value)
+ 0.13
DP-16 Conforms Conforms 1.07 g
Unit: mm
10.06 10.5 Max 16 9
5.5
1
*0.22 ± 0.05 0.20 ± 0.04
8 0.80 Max
2.20 Max
0.20 7.80 + – 0.30
1.15 0° – 8° 0.70 ± 0.20
1.27 *0.42 ± 0.08 0.40 ± 0.06
0.12 M
Hitachi Code JEDEC EIAJ Weight .