HD74ALVCH162835

HD74ALVCH162835 18-bit Universal Bus Drivers with 3-state Outputs ADE-205-189B (Z) 3rd. Edition December 1999 Description Data flow from A to Y is controlled by the output enable (OE ). The device operates in the transparent mode when LE is high. The A data is latched if CLK is held at a high or low logic level. If LE is low, the A bus data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±12 mA (@V CC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors All outputs have equivalent 26 Ω series resistors, so no external resistors are required. HD74ALVCH162835 Function Table Inputs OE H L L L L L L LE X H H L L L L CLK X X X ↑ ↑ H L A X L H L H X X Z L H L H Y0 Y0 *1 *2 Output Y H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established, provided that CLK is high before LE goes low. 2. Output level before the indicated steady state input conditio...