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HD74ALVCH16374 Dataheets PDF



Part Number HD74ALVCH16374
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description 16-bit D-type Flip Flops with 3-state Outputs
Datasheet HD74ALVCH16374 DatasheetHD74ALVCH16374 Datasheet (PDF)

HD74ALVCH16374 16-bit D-type Flip Flops with 3-state Outputs ADE-205-123B (Z) 3rd. Edition December 1999 Description The HD74ALVCH16374 has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic.

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HD74ALVCH16374 16-bit D-type Flip Flops with 3-state Outputs ADE-205-123B (Z) 3rd. Edition December 1999 Description The HD74ALVCH16374 has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@V CC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors. HD74ALVCH16374 Function Table Inputs OE H L L L H: L: X: Z: ↑: Q0 : CK X ↑ ↑ H or L D X L H X Output Q Z L H Q0 High level Low level Immaterial High impedance Low to high transition Level of Q before the indicated steady input conditions were established. 2 HD74ALVCH16374 Pin Arrangement 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 G Q G Q CK D CK D G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q CK D CK D CK D CK D CK D CK D CK D CK D CK D CK D CK D CK D 48 1CK 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VCC 30 2D5 29 2D6 28 GND 27 2D7 26 2D8 25 2CK CK D CK D (Top view) 3 HD74ALVCH16374 Absolute Maximum Ratings Item Supply voltage range Input voltage *1 *1, 2 Symbol VCC VI VO I IK I OK IO I CC or IGND PT Tstg Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VCC+0.5 –50 ±50 ±50 ±100 0.85 –65 to +150 Unit V V V mA mA mA mA W °C Conditions Output voltage Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation at Ta = 55°C (in still air) *3 Storage temperature Notes: VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TSSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maxim.


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