HD74ALVCH16825

HD74ALVCH16825 18-bit Buffers / Drivers with 3-state Outputs ADE-205-172A (Z) 2nd. Edition December 1999 Description The HD74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 9-bit buffers or one 18bit buffer. It provides true data. The 3-state control gate is a 2-input AND gate with active low inputs so that if either output enable (OE1 or OE2) input is high, all nine affected outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@V CC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Function Table Inputs OE1 L L H X H : High level L : Low level X : Immaterial Z : High impedance OE2 L L X H A L H X X L H Z Z Output Y HD74ALVCH16825 Pin Arrangement 1OE1 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 1Y5 8 1Y6 9 1Y7 10 GND 11 1Y8 12 1Y9 13 GND 14 GND 15 2Y1 16 2Y2 17 GND 18 2Y3 19 2Y4 20 2Y5 21 VCC 22 2Y6 23 2Y7 24 GND 25 2Y8 26 2Y9 27 2OE1 28 56 1OE2 55 1A1 54 1A2 53 GND 52 1A3 51 1A4 50 VCC 49 1A5 48 1A6 47 1A7 46 GND 45 1A8 44 1A9 43 GND 42 GND 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 2A5 35 VCC 34 2A6 33 2A7 32 GND 31 2A8 30 2A9 29 2OE2 (Top vie...