HD74ALVCH16827

HD74ALVCH16827 20-bit Buffers / Drivers with 3-state Outputs ADE-205-140B (Z) 3rd. Edition December 1999 Description The HD74ALVCH16827 is composed of two 10-bit sections with separated output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is high, the outputs of that 10-bit buffer section are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@V CC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Function Table Inputs OE1 L L H X H : High level L : Low level X : Immaterial Z : High impedance OE2 L L X H A L H X X L H Z Z Output Y HD74ALVCH16827 Pin Arrangement 1OE1 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 1Y5 8 1Y6 9 1Y7 10 GND 11 1Y8 12 1Y9 13 1Y10 14 2Y1 15 2Y2 16 2Y3 17 GND 18 2Y4 19 2Y5 20 2Y6 21 VCC 22 2Y7 23 2Y8 24 GND 25 2Y9 26 2Y10 27 2OE1 28 56 1OE2 55 1A1 54 1A2 53 GND 52 1A3 51 1A4 50 VCC 49 1A5 48 1A6 47 1A7 46 GND 45 1A8 44 1A9 43 1A10 42 2A1 41 2A2 40 2A3 39 GND 38 2A4 37 2A5 36 2A6 35 VCC 34 2A7 33 2A8 32 GND 31 2A9 30 2A10 29 2OE2 (Top view) 2 HD74ALVCH16827 Absolute Maximum Ratings Item Supply ...