HD74HC163 Clear Datasheet

HD74HC163 Datasheet, PDF, Equivalent


Part Number

HD74HC163

Description

Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear)

Manufacture

Hitachi Semiconductor

Total Page 16 Pages
Datasheet
Download HD74HC163 Datasheet


HD74HC163
HD74HC160/HD74HC161/
HD74HC162/HD74HC163
Synchronous Decade Counter (Direct Clear)
Synchronous 4-bit Binary Counter (Direct Clear)
Synchronous Decade Counter (Synchronous Clear)
Synchronous 4-bit Binary Counter (Synchronous Clear)
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the
HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waveform.
These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte
rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs
is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive
edge of clock the count operation will be unaffected.
All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162
and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive
edge of clock while the clear input is held low.
The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the
counter is cleared immediately regardless of the clock.
Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy
cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the
Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows.
This pulse is approximately equal in duration to the high level portion of the QA outputs. The Ripple Carry
output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
Features
High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max

HD74HC163
HD74HC160/HD74HC161/HD74HC162/HD74HC163
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Clock
Clear*1
L
Load
X
Enable P
X
Enable T
X
Outputs
Qn
Reset-clear
H L X X Load input data
H H H H Count
H H L X No count
H H X L No count
Note: 1. 162 and 163 Only-160 and 161 are Asynchronous Clear Devices
Decade Counter
Binary Counter
Asynchronous clear
HD74HC160P
HD74HC161P
Synchronous clear
HD74HC162P
HD74HC163P
Pin Arrangement
Clear 1
Clock 2
A3
B4
Data
Inputs C 5
D6
Enable P 7
GND 8
CLR
CK Ripple
Carry
A QA
B QB
C QC
D QD
PT
Load
(Top view)
16 VCC
15
Ripple
Carry Output
14 QA
13 QB
12 QC
Outputs
11 QD
10 Enable T
9 Load
2


Features HD74HC160/HD74HC161/ HD74HC162/HD74HC163 Synchronous Decade Counter (Direct Cle ar) Synchronous 4-bit Binary Counter (D irect Clear) Synchronous Decade Counter (Synchronous Clear) Synchronous 4-bit Binary Counter (Synchronous Clear) Des cription The HD74HC160 and the HD74HC16 2 are 4 bit decade counters, and the HD 74HC161 and the HD74HC163 are 4 bit bin ary counters All flip-flops are clocked simultaneously on the low to high to t ransition (positive edge) of the clock input waveform. These counters may be p reset using the load input. Presetting of all four flip-flops is synchronous t o thte rising edge of clock. When load is held low counting is disabled and th e data on the A, B, C, and D inputs is loaded into the counter on the rising e dge of clock. If the load input is take n high before the positive edge of cloc k the count operation will be unaffecte d. All of these counters may be cleared by utilizing the clear input. The clea r function on the HD74HC162 and HD74HC163 counters are synchron.
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