HD74HC237

HD74HC237 3-to-8-line Decoder/Demultiplexer with Address Latch Description The HD74HC237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then by using one of the Chip Selects as a data input while holding the other one active. The HD74HD237 is the noninverting version of the HD74HC137. Features High Speed Operation: tpd (Data to Y) = 19 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC237 Function Table Inputs Enable GL X X L L L L L L L L H G1 X L H H H H H H H H H G2 H X L L L L L L L L L Select C X X L L L L H H H H X B X X L L H H L L H H X A X X L H L H L H L H X Outputs Y0 L L H L L L L L L L Y1 L L L H L L L L L L Y2 L L L L H L L L L L Y3 L L L L L H L L L L Y4 L L L L L L H L L L Y5 L L L L L L L H L L Y6 L L L L L L L L H L Y7 L L L L L L L L L H Output corresponding to stored address H; all others L Pin Arrangement A B C GL G2 G1 Y7 GND 1 2 3 4 5 6 7 8 (Top view) B C GL G2 G1 Y7 A Y0 Y1 Y2 Y3 Y4 Y5 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 Y6 2 HD74HC237 Lo...