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H5TC2G63FFR-xxI Dataheets PDF



Part Number H5TC2G63FFR-xxI
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 2Gb DDR3L SDRAM
Datasheet H5TC2G63FFR-xxI DatasheetH5TC2G63FFR-xxI Datasheet (PDF)

2Gb DDR3L SDRAM 2Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC2G83FFR-xxA H5TC2G83FFR-xxI H5TC2G83FFR-xxL H5TC2G83FFR-xxJ H5TC2G63FFR-xxA H5TC2G63FFR-xxI H5TC2G63FFR-xxL H5TC2G63FFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Nov. 2012 1 Revision History Revision No. 1.0 History Official version release Draft Date Nov. 2012 Remark Rev. 1.0 / Nov. 2012 2 Description The H5TC2G83FFR-xxA(I,L,J) and H5TC2G63FFR-xxA(I,L,J) are.

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2Gb DDR3L SDRAM 2Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC2G83FFR-xxA H5TC2G83FFR-xxI H5TC2G83FFR-xxL H5TC2G83FFR-xxJ H5TC2G63FFR-xxA H5TC2G63FFR-xxI H5TC2G63FFR-xxL H5TC2G63FFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Nov. 2012 1 Revision History Revision No. 1.0 History Official version release Draft Date Nov. 2012 Remark Rev. 1.0 / Nov. 2012 2 Description The H5TC2G83FFR-xxA(I,L,J) and H5TC2G63FFR-xxA(I,L,J) are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and 13 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commerical Temperature (0oC ~ 85 oC) Industrial Temperature(-40oC ~ 95 oC) • JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 1.0 / Nov. 2012 3 ORDERING INFORMATION Part No. H5TC2G83FFR-*xxA H5TC2G83FFR-*xxI H5TC2G83FFR-*xxL H5TC2G83FFR-*xxJ H5TC2G63FFR-*xxA H5TC2G63FFR-*xxI H5TC2G63FFR-*xxL H5TC2G63FFR-*xxJ 128M x 16 Low Power Consumption (IDD6 Only) 256M x 8 Low Power Consumption (IDD6 Only) Normal Consumption Configuration Power Consumption Normal Consumption Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 96ball FBGA 78ball FBGA Package * xx means Speed Bin Grade OPERATIN.


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