HD74HC563

HD74HC563/HD74HC573 Octal Transparent Latches (with 3-state outputs) Description When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Output Control L L L H Q0 : Q0 : Latch Enable H H L X Data H L X X HD74HC563 L H Q0 Z HD74HD573 H L Q0 Z level of Q before the indicated Steady-sate input conditions were established. complement of Q 0 or level of Q before the indicated Steady-state input conditions were established. HD74HC563/HD74HC573 Pin Arrangement HD74HC563 Output 1 Control 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 Latch Enable (Top view) 2 HD74HC563/HD74HC573 HD74HC573 Output 1 Control 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND...