HD74HC592

HD74HC592 8-bit Register/Binary Counter Description The HD74HC592 consists of a parallel input, 8-bit storage register feeding an 8-bit binary counter. Both the register and the counter have individual positive edge-triggered clocks. In addition, the counter has direct load and clear functions. Expansion is easily accomplished by connecting RCO of the first stage to the count enable of the second stage, etc. Features High Speed Operation: tpd (CCK to RCO) = 24 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs RCK X X CLoad L H H H X X X H H H CCLR H L H H H H H CCKEN X X X X L L H X CCK X X X X Function Regiater data loaded into counter Counter clear Input data A to H stored into register No change in register Count up No count No cont RCO = QA’QB’QC’QD’QE’QF’QG’QH’ (CCKEN) (QA’ to QH’: Output of Internal Counter) HD74HC592 Pin Arrangement B 1 C 2 D 3 E 4 F 5 G 6 H 7 GND 8 (Top view) 16 VCC 15 A 14 C Load 13 RCK 12 CCKEN 11 CCK 10 CCLR 9 RCO 2 Logic Diagram CCKEN CLOAD CCLR CLR RCK CCK CCK CCK G H D RCK RCK RCK D C E B A F D D D D D D D RCK RCK RCK RCK RCK RCK RCK RCK RCK RCK RCK RCK LD RCK LD CLR CCK CCK T Q D LD CLR CCK CCK T D Q LD CLR CCK CCK T D Q LD CLR CCK CCK T D Q LD CLR CCK CCK T D Q LD CLR CCK CCK T D Q LD CLR CCK CCK T D Q HD74HC592 LD CLR C...