HD74HC669 Counter Datasheet
Synchronous UP/Down Decade/4-bit binary Counter
|Total Page||14 Pages|
Synchronous UP/Down Decade Counter
Synchronous Up/Down 4-bit binary Counter
This synchronous presettable decade counter features an internal carry look-ahead for cascading in high-
speed counting applications. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-
enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that
are normally associated with asynchronous (ripple-clock) counters.
A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the
clock waveform. This counter is fully programmable; that is, the outputs may each be preset to either level.
The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count enable inputs and a carry
output. Both count enable inputs (P and T) must be low to count. The direction of the count is determined
by the level of the up/down input. when the input is high, the counter counts up; when low, it counts down.
Input T is fed forward to enable the carry output. The carry output thus enabled will produce a low-level
output pulse with a duration approximately equal to the high portion of the QA output when counting up
and approximately equal to the low portion of the QA output when counting down. This low level overflow
carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are
allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transission-
line effects, thereby simplifying system design. This counter features a fully independent clock circuit.
Changes at control inputs (enable P, Enable T, load, up/down) that will modify the operating mode have no
effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable setup and hold times.
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
10 Enable T
|Features||HD74HC668/HD74HC669 Synchronous UP/Down Decade Counter Synchronous Up/Down 4-bi t binary Counter Description This sync hronous presettable decade counter feat ures an internal carry look-ahead for c ascading in highspeed counting applicat ions. Synchronous operation is provided by having all flip-flops clocked simul taneously so that the outputs change co incident with each other when so instru cted by the countenable inputs and inte rnal gating. This mode of operation hel ps eliminate the output counting spikes that are normally associated with asyn chronous (ripple-clock) counters. A buf fered clock input triggers the four mas ter-slave flip-flops on the rising (pos itive going) edge of the clock waveform . This counter is fully programmable; t hat is, the outputs may each be preset to either level. The load input circuit ry allows loading with the carry-enable output of cascaded counters. As loadin g is synchronous, setting up a low leve l at the load input disables the counter and causes the outputs.|
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