Flash Memory. Pm25LD512 Datasheet

Pm25LD512 Memory. Datasheet pdf. Equivalent

Pm25LD512 Datasheet
Recommendation Pm25LD512 Datasheet
Part Pm25LD512
Description 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory
Feature Pm25LD512; 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bu.
Manufacture Chingis Technology
Datasheet
Download Pm25LD512 Datasheet




Chingis Technology Pm25LD512
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial
Flash Memory With 100 MHz Dual-Output SPI Bus
Interface
Pm25LD512/010/ 020
FEATURES
Single Power Supply Operation
- Low voltage range: 2.3 V – 3.6 V
• Memory Organization
- Pm25LD512: 64K x 8 (512 Kbit)
- Pm25LD010: 128K x 8 (1 Mbit)
- Pm25LD020: 256K x 8 (2 Mbit)
Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4KByte sectors / Two uniform
32KByte blocks
- 1Mb : Uniform 4KByte sectors / Four uniform
32KByte blocks
- 2Mb : Uniform 4KByte sectors / Four uniform
64KByte blocks
• Low standby current 1uA (Typ)
Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
Sector, Block or Chip Erase Operation
- Maximum 10 ms sector, block or chip erase
Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow
partial or entire memory to be configured as read-
only
High Product Endurance
- Guaranteed 200,000 program/erase cycles per
single sector
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LD040
- 8-pin 300mil PDIP for Pm25LD040
- 8-contact WSON
- 8-pin TSSOP
- Lead-free (Pb-free), halogen-free package
GENERAL DESCRIPTION
The Pm25LD512/010/020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing
single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100
MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating
voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The Pm25LD512/010/020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output
(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all
recognized command codes and operations. The dual-output fast read operation provides and effective serial
data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in
one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte
blocks.(Pm25LD020 is uniform 4 KByte sectors or uniform 64 KByte).
The Pm25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures
between -40°C to +105°C.
Confidential information
Chingis Technology Corp.
1 DRAFT Date: August, 2010, Rev:0.4



Chingis Technology Pm25LD512
PRODUCT ORDERING INFORMATION
Pm25LDxxx - S C E
Pm25LD512/010/ 020
Environmental Attribute
E = Lead-free (Pb-free) and Halogen- free
package
Temperature Range
C = Commercial Grade (-40°C to +105°C)
Package Type
S = 8-pin SOIC 150mil (8S)
B = 8-pin SOIC 208mil (8B)
P = 8-pin PDIP 300 mil (8P)
K = 8-contact WSON (8K)
pFlash Device Number
Pm25LD512/010/020
Part Number
Operating Frequency (MHz) Package
Temperature Range
Pm25LD512-SCE
Pm25LD010-SCE
Pm25LD020-SCE
Pm25LD512-KCE
Pm25LD010-KCE
Pm25LD020-KCE
Pm25LD040-PCE
Pm25LD040-BCE
Pm25LD512-DCE
Pm25LD010-DCE
Pm25LD020-DCE
100
8S
150mil SOIC
8K WSON
100 (Back Side
Metal)
Commercial Grade
(-40oC to +105oC)
100 8P 300mil PDIP
100 8B 208mil SOIC
100 8-pin TSSOP
Confidential information
Chingis Technology Corp.
2 DRAFT Date: August, 2010, Rev:0.4



Chingis Technology Pm25LD512
CONNECTION DIAGRAMS
CE# 1
8
SO 2
7
Vcc
HOLD#
WP#
GND
36
45
8-Pin SOIC
SCK
SIO
Pm25LD512/010/ 020
CE# 1
SO 2
WP# 3
GND 4
8 Vcc
7 HOLD#
6 SCK
5 SIO
8-Contact WSON
CE#
SO
WP#
GND
1
2
3
4
8 Vcc
7 HOLD#
6 SCK
5 SIO
8-Pin TSSOP
CE# 1
SO 2
WP# 3
GND 4
8 Vcc
7 HOLD#
6 SCK
5 SIO
PIN DESCRIPTIONS
8-Pin PDIP
SYMBOL TYPE
DESCRIPTION
CE#
SCK
SIO
SO
GND
Vcc
WP#
HOLD#
INPUT
INPUT
INPUT/OUTPUT
OUTPUT
INPUT
INPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (SlO), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
Serial Data Input/Output
Serial Data Output
Ground
Device Power Supply
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends
on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is
high, the devices are not write-protected.
Hold: Pause serial communication by the master device without resetting
the serial sequence.
Confidential information
Chingis Technology Corp.
3 DRAFT Date: August, 2010, Rev:0.4







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