DatasheetsPDF.com

NJU26041-01A Dataheets PDF



Part Number NJU26041-01A
Manufacturers New Japan Radio
Logo New Japan Radio
Description Digital Signal Processor
Datasheet NJU26041-01A DatasheetNJU26041-01A Datasheet (PDF)

NJU26041-01A ■ General Description Digital Signal Processor for TV ■Package The NJU26041-01A is a high performance 24-bit digital signal processor. The NJU26041-01A provides ‘eala’ 3D Surround function, ‘ealaBass’ Dynamic Bass Boost function, Dialogue Boost, 3-bands 2-stages AGC, and Tone Control. These kinds of sound functions are suitable for TV, mini-component, CD radio-cassette, speakers system and other audio products. ■ FEATURES - Software • 3D sound : eala(NJRC Original Surround) • So.

  NJU26041-01A   NJU26041-01A



Document
NJU26041-01A ■ General Description Digital Signal Processor for TV ■Package The NJU26041-01A is a high performance 24-bit digital signal processor. The NJU26041-01A provides ‘eala’ 3D Surround function, ‘ealaBass’ Dynamic Bass Boost function, Dialogue Boost, 3-bands 2-stages AGC, and Tone Control. These kinds of sound functions are suitable for TV, mini-component, CD radio-cassette, speakers system and other audio products. ■ FEATURES - Software • 3D sound : eala(NJRC Original Surround) • Sound Enhancement: : ealaBass (NJRC Original Dynamic Bass Boost) : Dialogue Boost (NJRC Original Dialogue Boost) • 3-bands 2-stages AGC • Tone Control • Master Volume / Balance control • WatchDog Clock Output NJU26041V - Hardware • 24bit Fixed-point Digital Signal Processing • Maximum System Clock Frequency : 38MHz Max. • Digital Audio Interface : 1 Input port / 2 Output ports • Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs • Master / Slave Mode : Master Mode MCK 1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs • Power Supply : 3.3V • Input terminal : 5V Input tolerant • Package : SSOP32 (Pb-Free) • Two kinds of micro computer interface : I2C bus (standard-mode/100kbps, Fast-mode/400kbps) : Serial interface (4 lines: clock, enable, input data, output data) The detail hardware specification is described in the “ NJU26041 Series Hardware Data Sheet”. Ver.2007-10-13 -1- NJU26041-01A ■ Function Block Diagram SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSb ALU RESETb MCK CLKOUT CLK GPIO INTERFACE TIMING GENERATOR SERIAL HOST INTERFACE 24Bit Fixed-point DSP Core PROGRAM CONTROL 24Bit x 24Bit MULTIPLIER SERIAL AUDIO INTERFACE SDI0 SDO0-1 BCKI LRI BCKO LRO ADDRESS GENERATION UNIT WDC MUTEb PROC SEL DATA RAM FIRMWARE OTP/RAM Fig. 1 NJU26041-01A Block Diagram ■ DSP Block Diagram Low Trim AGC LPF Middle Trim AGC BPF SDI0 AGC HPF High Trim Input Trim Dialogue Boost eala Tone Control Master Volume ealaBass LR0 Trim SDO0 LR1 Trim SDO1 Fig. 2 NJU26041-01A Function Diagram -2- Ver.2007-10-13 NJU26041-01A ■ Pin Configuration VDD SDA/SDOUT SCL/SCK AD1/SDIN AD2/SSb RESETb VDD VDD VSS CLKOUT CLK TEST TEST SDI0 LRI BCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NJU26041-01A 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS TEST TEST SEL PROC MUTEb WDC VDD VSS TEST MCK TEST SDO1 SDO0 LRO BCKO SSOP32 Fig. 3 NJU26041-01A Pin Configuration Ver.2007-10-13 -3- NJU26041-01A ■ Pin Description Table 1 Pin Description Pin No. Symbol 1, 7, 8, 25 VDD 2 3 4 5 6 9, 24, 32 10 11 12, 13 14 15 16 17 18 19 20 21 22 23, 30, 31 26 27 28 29 Note : I IO OD I/O+ I/O SDA / SDOUT Power Supply +3.3V / 4-Wire Serial Output I2C I/O This pin requires a pull-up resistance in both I2C bus and 4-Wire OD serial mode. 2 I I C Clock / Serial Clock I I2C Address / Serial Input I I2C Address / Serial Enable I Reset (RESETb=’Low’ : DSP Reset) GND O OSC Output I OSC Clock Input I for Test (connected to VSS) I Audio Data Input 0 I LR Clock Input I .


MB85RC256V NJU26041-01A NJU26041


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)