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HD74HC91
8-bit Shift Register
Description
This serial-in, serial-out, 8-bit shift register is composed of eight R-S master-slave flip-flops, input gating, and a clock drive. Single-rail data and input control are gated through inputs A and B and an internal inverter to form the complementary inputs to the first bit of the shift register. Drive for the internal common clock line is provided by an inverting clock driver. This clock pulse inverter/driver causes these circuits to shift information one bit on the positive edge of an input clock pulse.
Features
• • • • • High Speed Operation: tpd (Data Word Input to Output) = 21 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs tn A H L X X : tn : t n + 8: B H X L Irrelevant Reference bit time, clock low Bit time after 8 low-to-high clock transitions Outputs tn + 8 QH H L L QH L H H
HD74HC91
Pin Arrangement
NC NC NC NC Vcc NC NC
1 2 3 4 5 6 7 (Top View) CK QH QH A B
14 13 12 11 10 9 8
QH QH A Inputs B GND Clock NC
2
HD74HC91
DC Characteristics
Ta = 25°C Item Input voltage Symbol VIH Ta = –40 to +85°C Max — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 mA I OL = 5.2 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = –4 mA I OH = –5.2 mA Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = –20 µA V Unit V Test Conditions
VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 — 3.15 — 4.2 — — — — — — — — — — 0.5 1.5 3.15 4.2 —
VIL
2.0 4.5 6.0
1.35 — 1.8 — 1.9 4.4 5.9 4.13 5.63 — — —
Output voltage
VOH
2.0 4.5 6.0 4.5 6.0
1.9 2.0 — 4.4 4.5 — 5.9 6.0 — 4.18 — 5.68 — — — — — — — — — —
VOL
2.0 4.5 6.0 4.5 6.0
0.0 0.1 0.0 0.1 0.0 0.1 — — — —
0.26 — 0.26 — ±0.1 — 4.0 —
Input current Quiescent supply current
Iin I CC
6.0 6.0
3
HD74HC91
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C Item Maximum clock frequency Symbol f max Ta = –40 to +85°C Max 4 20 24 265 53 45 265 53 45 — — — — — — — — — 95 19 16 10 pF ns ns ns ns Clock ns ns Unit MHz Test Conditions
VCC (V) Min Typ Max Min 2.0 4.5 6.0 — — — — — — — — — — — — — 21 — — 21 — 5 25 29 — — —
Propagation delay t PLH time
2.0 4.5 6.0
210 — 42 36 — —
t PHL
2.0 4.5 6.0
210 — 42 36 — — — — — — — — — 75 15 13 10 — — 156 31 26 156 31 26 5 5 5 — — — —
Pulse width
tw
2.0 4.5 6.0
125 — 25 21 9 —
Set up time
t su
2.0 4.5 6.0
125 — 25 21 5 5 5 — — — — 1 — — –1 — — 5 — 5
Hold time
th
2.0 4.5 6.0
Output rise/fall time
t TLH t THL
2.0 4.5 6.0
Input capacitance
Cin
—
4
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.10
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-14 Conforms Conforms 0.97 g
Unit: mm
10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8°
+ 0.20
1.42 Max
1.27 *0.4.