Document
PALCE22V10 is a replacement device for PALC22V10, PALC22V10B, and PALC22V10D.
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PALCE22V10
Flash-erasable Reprogrammable CMOS PAL® Device
Features
• Low power — 90 mA max. commercial (10 ns) — 130 mA max. commercial (5 ns) • CMOS Flash EPROM technology for electrical erasability and reprogrammability • Variable product terms — 2 ×(8 through 16) product terms • User-programmable macrocell — Output polarity control — Individually selectable for registered or combinatorial operation • Up to 22 input terms and 10 outputs • DIP, LCC, and PLCC available — 5 ns commercial version 4 ns tCO 3 ns tS 5 ns tPD 181-MHz state machine — 10 ns military and industrial versions 7 ns tCO 6 ns tS 10 ns tPD 110-MHz state machine — 15-ns commercial, industrial, and military versions — 25-ns commercial, industrial, and military versions • High reliability — Proven Flash EPROM technology — 100% programming and functional testing
Logic Block Diagram (PDIP/CDIP)
VSS 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 CP/I 1
PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 16 16 14 12 10 8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13 I
14 I/O9
15 I/O8
16 I/O 7
17 I/O6
18 I/O5
19 I/O4
20 I/O3
21 I/O2
22 I/O1
23 I/O0
24 V CC
Pin Configuration
I I CP/I NC VCC I/O0 I/O1
4 3 2 1 282726 I I I NC I I I 5 6 7 8 9 10 11 12131415161718 V SS NC I/O9 I/O8 I I I 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 I I I NC I I I 5 6 7 8 9 10 11
I I CP/I NC V CC I/O0 I/O1 4 3 2 1 2827 26 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 121314 1516 1718 V SS NC I I I
LCC Top View
PLCC Top View
Cypress Semiconductor Corporation Document #: 38-03027 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134 • 408-943-2600 Revised April 9, 2004
I/O9 I/O8
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Selection Guide
Generic Part Number PALCE22V10-5 PALCE22V10-7 PALCE22V10-10 PALCE22V10-15 PALCE22V10-25 5 7.5 10 15 25 10 15 25 tPD ns Com’l Mil/Ind Com’l 3 5 6 10 15 6 10 15 tS ns Mil/Ind 4 5 7 8 15 7 8 15 tCO ns Com’l Mil/Ind
PALCE22V10
ICC mA Com’l 130 130 90 90 90 150 120 120 Mil/Ind
Functional Description
The Cypress PALCE22V10 is a CMOS Flash-erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell. The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The PALCE22V10 can be electrically erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individually. Each of the ten potential outputs may be specified as “registered” or “combinatorial.” Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through “array” configurable “output enable” for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array. PALCE22V10 features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PALCE22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array complexity. Since each of the ten output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to twelve inputs and ten outputs are possible. The ten potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing curre.