PAL Device. PALCE22V10 Datasheet

PALCE22V10 Device. Datasheet pdf. Equivalent

Part PALCE22V10
Description 24-Pin EE CMOS Versatile PAL Device
Feature FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25 PALCE22V10 Family 24-Pin EE CMOS Versat.
Manufacture AMD
Datasheet
Download PALCE22V10 Datasheet



PALCE22V10
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/20/25
PALCE22V10 Family
24-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s As fast as 5-ns propagation delay and
142.8 MHz fMAX (external)
s Low-power EE CMOS
s 10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
s Varied product term distribution allows up to
16 product terms per output for complex
functions
s Peripheral Component Interconnect (PCI)
compliant (-5/-7/-10)
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic
for replacing conventional SSI/MSI gates and flip-flops
at a reduced chip count.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, and active
BLOCK DIAGRAM
CLK/I0
1
s Global asynchronous reset and synchronous
preset for initialization
s Power-up reset for initialization and register
preload for testability
s Extensive third-party software and programmer
support through FusionPLD partners
s 24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flat-
pack and 28-pin PLCC and LCC packages save
space
s 5-ns and 7.5-ns versions utilize split lead-
frames for improved performance
high or active low. The output configuration is
determined by two bits controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PALCE22V10 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
I1 - I11
11
8 10
Programmable
AND Array
(44 x 132)
12 14 16 16 14 12 10
8
RESET
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
PRESET
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5
Publication# 16564 Rev. D Amendment /0
Issue Date: February 1996
I/O6 I/O7 I/O8
I/O9 16564D-1
2-217



PALCE22V10
AMD
CONNECTION DIAGRAMS
Top View
SKINNYDIP/SOIC/FLATPACK
PLCC/LCC
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O9
22 I/O8
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
16 I/O2
15 I/O1
14 I/O0
13 I11
4 3 2 1 28 27 26
I3 5
I4 6
I5 7
NC 8
25
24
23
22
I6 9
21
I7 10
20
I8 11
19
12 13 14 15 16 17 18
I/O7
I/O6
I/O5
GND/NC*
I/O4
I/O3
I/O2
16564D-2
16564D-3
* For -5, this pin must be grounded for guaranteed data sheet performance. If not grounded, AC timing may degrade
by about 10%.
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
NC = No Connect
VCC = Supply Voltage
2-218
PALCE22V10 Family





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