Document
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25
PALCE22V10 Family
24-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s As fast as 5-ns propagation delay and 142.8 MHz fMAX (external) s Low-power EE CMOS s 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs s Varied product term distribution allows up to 16 product terms per output for complex functions s Peripheral Component Interconnect (PCI) compliant (-5/-7/-10) s Global asynchronous reset and synchronous preset for initialization s Power-up reset for initialization and register preload for testability s Extensive third-party software and programmer support through FusionPLD partners s 24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flatpack and 28-pin PLCC and LCC packages save space s 5-ns and 7.5-ns versions utilize split leadframes for improved performance
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell. AMD’s FusionPLD program allows PALCE22V10 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar.
BLOCK DIAGRAM
CLK/I0 1 11 I1 - I11
Programmable AND Array (44 x 132)
8 10 12 14 16 16 14 12 10 8
RESET
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
16564D-1
Publication# 16564 Rev. D Issue Date: February 1996
Amendment /0
2-217
AMD
CONNECTION DIAGRAMS Top View SKINNYDIP/SOIC/FLATPACK
I2 I1 CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I11
16564D-2
PLCC/LCC
CLK/I0 V.