AT45DB161E. 45DB161E Datasheet

45DB161E AT45DB161E. Datasheet pdf. Equivalent

Part 45DB161E
Description AT45DB161E
Feature AT45DB161E 16-Mbit DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum SPI Serial Flash Memory D.
Manufacture Adesto
Datasheet
Download 45DB161E Datasheet



45DB161E
AT45DB161E
16-Mbit DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum
SPI Serial Flash Memory
Features
DATASHEET
Single 2.3V - 3.6V or 2.5V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports RapidSoperation
Continuous read capability through entire array
Up to 85MHz
Low-power read option up to 15MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the main memory array
Flexible programming options
Byte/Page Program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible erase options
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (128KB)
Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
400nA Ultra-Deep Power-Down current (typical)
3μA Deep Power-Down current (typical)
25μA Standby current (typical at 20MHz)
11mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide and 0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)
8782G–DFLASH–10/2013



45DB161E
Description
The Adesto® AT45DB161E is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited for
a wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E also supports the
RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized
as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB161E also contains two
SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being
reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data
stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation
(bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the
Adesto DataFlash® uses a serial interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,
and reduces package size. The device is optimized for use in many commercial and industrial applications where
high-density, low-pin count, low-voltage, and low-power are essential.
To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages for
programming. The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and program
and read operations. The AT45DB161E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
1. Pin Configurations and Pinouts
Figure 1-1. Pinouts
8-lead SOIC
Top View
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
8-pad UDFN
Top View
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
8-ball UBGA
Top View
SCK GND VCC
CS NC WP
SO SI RST
Note: 1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.
This pad can be a “no connect” or connected to GND.
AT45DB161E
8782G–DFLASH–10/2013
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