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AT42QT1060 Dataheets PDF



Part Number AT42QT1060
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description 6-channel Sensor
Datasheet AT42QT1060 DatasheetAT42QT1060 Datasheet (PDF)

Features • Configurations: – Can be configured as a combination of keys and input/output lines • Number of Keys: – 2 to 6 • Number of I/O Lines: – 7, configurable for input or output, with PWM control for LED driving • Technology: – Patented spread-spectrum charge-transfer (direct mode) • Key Outline Sizes: – 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible Layers Required: – One Electrode Materials: – Etched copper – Silver – Carbon – Indium Tin .

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Features • Configurations: – Can be configured as a combination of keys and input/output lines • Number of Keys: – 2 to 6 • Number of I/O Lines: – 7, configurable for input or output, with PWM control for LED driving • Technology: – Patented spread-spectrum charge-transfer (direct mode) • Key Outline Sizes: – 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible Layers Required: – One Electrode Materials: – Etched copper – Silver – Carbon – Indium Tin Oxide (ITO) Panel Materials: – Plastic – Glass – Composites – Painted surfaces (low particle density metallic paints possible) Panel Thickness: – Up to 10 mm glass (electrode size dependent) – Up to 5 mm plastic (electrode size dependent) Key Sensitivity: – Individually settable via simple commands over serial interface Interface: – I2C-compatible slave mode (100 kHz). Discrete detection outputs Power: – 1.8V to 5.5V Package: – 28-pin 4 x 4 mm MLF RoHS compliant IC Signal Processing: – Self-calibration – auto drift compensation – noise filtering – Adjacent Key Suppression™ Applications: – Mobile appliances • • QTouch™ 6-channel Sensor IC AT42QT1060 • • • • • • • • 9505E–AT42–02/09 1. Pinout and Schematic 1.1 Pinout Configuration SNS0K 1 2 3 4 5 6 7 8 CHG SDA RST SCL SNS1K SNS2K VDD VSS IO5 IO6 SNS3K 28 27 26 25 24 23 22 21 20 19 IO4 SNS5K QT1060 15 9 10 11 12 13 14 IO3 SNS0 IO2 IO1 IO0 VSS VDD VDD SNS5 18 17 16 SNS4K SNS1 SNS3 SNS4 SNS2 1.2 Pin Descriptions Table 1-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Listing Name SNS1K SNS2K VDD VSS IO5 IO6 SNS3K SNS4K SNS5K SNS0 SNS1 SNS2 SNS3 SNS4 SNS5 VDD VDD Type IO IO P P IO IO IO IO IO IO IO IO IO IO IO P P Description To Cs capacitor and to key To Cs capacitor and to key Positive power pin Ground power pin IO Port Pin 5 IO Port Pin 6 To Cs capacitor and to key To Cs capacitor and to key To Cs capacitor and to key To Cs Capacitor To Cs Capacitor To Cs Capacitor To Cs Capacitor To Cs Capacitor To Cs Capacitor Positive power pin Positive power pin Leave open and set as output Leave open and set as output Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open If Unused, Connect To... Leave open Leave open 2 AT42QT1060 9505E–AT42–02/09 AT42QT1060 Table 1-1. Pin 18 19 20 21 22 23 24 25 26 27 28 Pin Listing (Continued) Name VSS IO0 IO1 IO2 CHG SDA SCL RST IO3 IO4 SNS0K I O OD Type P IO IO IO OD OD OD I IO IO IO Input only Output only, push-pull Open drain output Description Ground power pin IO Port Pin 0 IO Port Pin 1 IO Port Pin 2 Change line I2C-compatible Data line I2C-compatible Clock Line Reset, active low IO Port Pin 3 IO Port Pin 4 To Cs capacitor and to key IO P Leave open and set as output Leave open and set as output Leave open and set as output Leave open Resistor to Vdd or Vss only in standalone mode Resistor to Vdd or Vdd only in standalone mode Vdd Leave open and set as output Leave open and set as output Leave open Input and output Ground or power If Unused, Connect To... 3 9505E–AT42–02/09 1.3 Schematic Typical Circuit Vunreg Voltage Reg Figure 1-1. 100nF CB1 VDD Note: Bypass capacitor to be tightly wired between Vdd and Vss. Follow recommendations from regulator manufacturer for input and output capacitors. 16 3 17 VDD VDD VDD Rs5 25 SNS5K RST SNS5 SNS4K 9 15 8 14 7 13 2 12 1 11 28 10 KEY 5 Cs5 Rs4 KEY 4 Cs4 Rs3 6 5 27 IO6 IO5 IO4 IO3 IO2 IO1 IO0 SNS4 SNS3K SNS3 SNS2K SNS2 SNS1K SNS1 SNS0K SNS0 KEY 3 Cs3 Rs2 IO Port pins 26 21 20 19 KEY 2 Cs2 Rs1 KEY 1 Cs1 Rs0 KEY 0 Cs0 QT1060 VDD Rchg 100k Keep these parts close to the IC SDA 22 23 24 I C-compatible Data I C-compatible Clock in Standalone Mode 2 2 Change CHG SCL Note: The central pad on the underside of the chip is a Vss pin and should be connected to ground. VSS VSS SDA 23 18 4 VDD SCL 24 Note: In some systems it may be desirable to connect RST to the master reset signal. Suggested regulator manufacturers: • • • Torex (XC6215 series) Seiko (S817 series) BCDSemi (AP2121 series) Re Figure 1-1 check the following sections for component values: • • • • • Section 3.1 on page 9: Cs capacitors (Cs0 – Cs5) Section 3.2 on page 9: Series resistors (Rs0 – Rs5) Section 3.5 on page 10: Voltage levels Section 5.4 on page 16: SDA, SCL pull-up resistors (not shown) Section 3.3 on page 10: LED traces 4 AT42QT1060 9505E–AT42–02/09 AT42QT1060 2. Overview 2.1 Introduction The AT42QT1060 (QT1060) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed specifically for mobile phone applications. The device can sense from two to six keys; up to four keys can be disabled by not installing their respective sense capacitors (Cs). It also has up to seven configurable input/output lines, with Pulse Width Modulation (PWM) for LED driving. This device includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outp.


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