9LPRS525 Datasheet: ICS9LPRS525





9LPRS525 ICS9LPRS525 Datasheet

Part Number 9LPRS525
Description ICS9LPRS525
Manufacture Integrated Device Technology
Total Page 21 Pages
PDF Download Download 9LPRS525 Datasheet PDF

Features: DATASHEET 56-pin CK505 for Intel System s Recommended Application: 56-pin CK505 compatible clock, w/fully integrated V reg and series resistors on differentia l outputs Output Features: • 2 - CPU differential low power push-pull pairs • 7 - SRC differential push-pull pair s • 1 - CPU/SRC selectable differenti al low power push-pull pair • 1 - SRC /DOT selectable differential low power push-pull pair • 1 - SRC/SE selectabl e differential push-pull pair/Single-en ded outputs • 5 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key S pecifications: • CPU outputs cycle-cy cle jitter < 85ps • SRC output cycle- cycle jitter < 125ps • PCI outputs cy cle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on all outputs • SRC outputs meet PCIe Gen2 when sourced from PLL3 Pin Configuration PCI0/CR#_A 1 VDDPCI PCI1/CR#_B PCI2/TME PCI3/CFG0 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD4 8 USB_48MHz/FSLA GND48 VDD96IO DOTT_96_ LRS/SRCT0_LRS DOTC_96_LRS/SRCC0_LRS GND VDD SRCT1_LRS/SE1 SRCC1_LRS/SE2 GND VDDPLL3IO SRC.

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DATASHEET
56-pin CK505 for Intel Systems
ICS9LPRS525
Recommended Application:
56-pin CK505 compatible clock, w/fully integrated Vreg and series
resistors on differential outputs
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
• 5 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
• SRC outputs meet PCIe Gen2 when sourced from PLL3
Features/Benefits:
• Supports spread spectrum modulation, 0 to -0.5% down
spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FSLC2
B0b7
0
0
0
0
1
1
1
1
FSLB1
B0b6
0
0
1
1
0
0
1
1
FSLA1
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC PCI REF USB DOT
MHz MHz MHz MHz MHz
100.00 33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
PCI0/CR#_A 1
56 SCLK
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3/CFG0 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96IO 12
DOTT_96_LRS/SRCT0_LRS 13
DOTC_96_LRS/SRCC0_LRS 14
GND 15
VDD 16
SRCT1_LRS/SE1 17
SRCC1_LRS/SE2 18
GND 19
VDDPLL3IO 20
SRCT2_LRS/SATAT_LRS 21
SRCC2_LRS/SATAC_LRS 22
GNDSRC 23
SRCT3_LRS/CR#_C 24
SRCC3_LRS/CR#_D 25
VDDSRCIO 26
SRCT4_LRS 27
SRCC4_LRS 28
55 SDATA
54 REF0/FSLC/TEST_SEL
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUT0_LRS
45 CPUC0_LRS
44 GNDCPU
43 CPUT1_F_LRS
42 CPUC1_F_LRS
41 VDDCPUIO
40 NC
39 CPUT2_ITP_LRS/SRCT8_LRS
38 CPUC2_ITP_LRS/SRCC8_LRS
37 VDDSRCIO
36 SRCT7_LRS/CR#_F
35 SRCC7_LRS/CR#_E
34 GNDSRC
33 SRCT6_LRS
32 SRCC6_LRS
31 VDDSRC
30 PCI_STOP#/SRCT5_LRS
29 CPU_STOP#/SRCC5_LRS
56-SSOP & TSSOP
IDTTM PC MAIN CLOCK
1
1484C—04/20/10

                    
                    






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