56F807

56F807 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F807 Rev. 16 09/2007 freescale.com Document Revision History Version History Rev. 16 Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.” 56F807 General Description Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 60K × 16-bit words (120KB) Program Flash 2K × 16-bit words (4KB) Program RAM 8K × 16-bit words (16KB) Data Flash 4K × 16-bit words (8KB) Data RAM 2K × 16-bit words (4KB) Boot Flash Up to 64K × 16- bit words (128KB) each of external Program and Data memory Two 6 channel PWM Modules Four 4 channel, 12-bit ADCs Two Quadrature Decoders CAN 2.0 B Module Two Serial Communication Interfaces (SCIs) Serial Peripheral Interface (SPI) Up to four General Purpose Quad Timers JTAG/OnCETM port for debugging 14 Dedicated and 18 Shared GPIO lines 160-pin LQFP or 160 MAPBGA Packages 6 3 4 6 PWM Outputs Current Sense Inputs Fault Inputs PWM Outputs Current Sense Inputs Fault Inputs A/D1 A/D2 A/D1 A/D2 ADCA VREF ADCB VREF2 PWMA RSTO RESET IRQA EXTBOOT IRQB 6 JTAG/ OnCE Port VPP VCAPC VDD 2 8 VSS 10* Digital Reg VDDA...