CY7C038

25/0251 CY7C027/028 CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Features True Dual-Ported memory cells which allow simultaneous access of the same memory location 32K x 16 organization (CY7C027) 64K x 16 organization (CY7C028) 32K x 18 organization (CY7C037) 64K x 18 organization (CY7C038) 0.35-micron CMOS for optimum speed/power High-speed access: 12[1]/15/20 ns Low operating power — Active: ICC = 180 mA (typical) — Standby: ISB3 = 0.05 mA (typical) Fully asynchronous operation Automatic power-down Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flags for port-to-port communication Separate upper-byte and lower-byte control Dual Chip Enables Pin select for Master or Slave Commercial and industrial temperature ranges Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT7027 Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL OEL CEL CER CE0R CE1R LBR OER I/O8/9L–I/O15/17L [3] [2] 8/9 8/9 8/9 [2] I/O0L–I/O7/8L I/O Control I/O Control 8/9 I/O8/9L–I/O15/17R [3] I/O0L–I/O7/8R A0L–A14/15L [4] 15/16 Address Decode 15/16 True Dual-Ported RAM Array Address Decode 15/16 15/16 A0R–A14/15R [4] [4] A0L–A14/15L CEL OEL R/WL SEML BUSYL INTL UBL LBL [5] Interrupt Semaphore Arbitration A0R–A14/15R CER OER R/WR SEMR [5] [4] M/S 4. 5. BUSYR INTR...