ADSP-21160

a Preliminary Technical Data SUMMARY DSP Microcomputer ADSP-21160 KEY FEATURES High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication Super Harvard Architecture—four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backwards compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4 Mbit on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, & JTAG) CO RE PROCESSO R TI MER I NST RU C TI ON CACHE 32 x 48-BIT ADD R ADDR 80 MHz (12.5 ns) or 100 MHz (10 ns) core instruction rate Single-cycle instruction execution, including SIMD operations in both computational units 600 MFLOPS peak and 400 MFLOPS sustained performance (based on FIR) Dual Data Address Generators (DAGs) with modulo and bit-reverse addressing Zero-overhead looping and single-cycle loop setup, providing efficient program sequencing IEEE 1149.1 JTAG standard test access port and on-chip emulation 400-ball 27×27mm PBGA package DUAL-PORTED SRAM BLOCK 1 TW O I N DE P E N D E N T D U A L - P O R TE D B L O C K S PROCESSOR PORT DA TA DATA BLOCK 0 JTAG TE S T & EM U L A T I O N 6 I / O P O RT DATA DATA ADDR ADDR...