Document
SPN2054
N-Channel Enhancement Mode MOSFET
DESCRIPTION The SPN2054 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application, such as DC/DC converter and Desktop computer power management. The package is universally preferred for commercial industrial surface mount applications
APPLICATIONS • Power Management in Desktop Computer • DC/DC Converter
• LCD Display inverter
FEATURES 20V/12A,RDS(ON)=40mΩ@VGS=10V 20V/7A,RDS(ON)=45mΩ@VGS=4.5V 20V/4A,RDS(ON)=50mΩ@VGS=2.5V 20V/2A,RDS(ON)=60mΩ@VGS=1.8V Super high density cell design for extremely low
RDS (ON) Exceptional on-resistance and maximum DC
current capability TO-252-2L package design
PIN CONFIGURATION(TO-252-2L)
PART MARKING
2020/04/28 Ver.4
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SPN2054
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION Pin 1 2 3
Symbol G D S
Description Gate Drain
Source
ORDERING INFORMATION
Part Number
Package
SPN2054T252RGB
TO-252-2L
※ Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※ SPN2054T252RGB : Tape Reel ; Pb – Free ; Halogen - Free
Part Marking SPN2054
ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage Continuous Drain Current(TJ=150℃) Pulsed Drain Current
TA=25℃ TA=70℃
Continuous Source Current(Diode Conduction)
Power Dissipation
TA=25℃ TA=70℃
Operating Junction Temperature
Storage Temperature Range Thermal Resistance-Junction to Ambient
Symbol VDSS VGSS ID
IDM IS
PD TJ TSTG RθJA
Typical 20
±12 12 8 20
12 40 20 -55/150 -55/150 105
Unit V V A
A A
W ℃ ℃ ℃/W
2020/04/28 Ver.4
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SPN2054
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted)
Parameter Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate Leakage Current
Zero Gate Voltage Drain Current
Drain-Source On-Resistance
Forward Transconductance Diode Forward Voltage Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Time
Turn-Off Time
Symbol
Conditions
V(BR)DSS VGS=0V,ID=250uA
VGS(th) VDS=VGS,ID=250uA
IGSS VDS=0V,VGS=±12V
IDSS RDS(on)
gfs
VDS=20V,VGS=0V VDS=20V,VGS=0V TJ=55℃ VGS=10V,ID=12A VGS=4.5V,ID=7A VGS=2.5V,ID=4A VGS=1.8V,ID=2A VDS=5V,ID=-3.6A
VSD IS=7A,VGS=0V
Qg Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf
VDS=10V,VGS=4.5V ID=12A
VDS=10V,VGS=0V f=1MHz
VDD=10V,RL=6Ω ID=1.0A,VGEN=4.5V RG=6Ω
Min. Typ Max. Unit
20 V
0.36
1.0
±100 nA
1 uA
5
0.031 0.040 0.035 0.045 Ω 0.040 0.050 0.048 0.060
10
S
0.95 1.2 V
4.8
8
1.0
nC
1.0
485
85
pF
40
8
14
12
18 nS
30
35
12
16
2020/04/28 Ver.4
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SPN2054
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2020/04/28 Ver.4
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SPN2054
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2020/04/.