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A3PN060 Dataheets PDF



Part Number A3PN060
Manufacturers Microsemi Corporation
Logo Microsemi Corporation
Description ProASIC3 nano Flash FPGAs
Datasheet A3PN060 DatasheetA3PN060 Datasheet (PDF)

Revision 11 ProASIC3 nano Flash FPGAs Features and Benefits Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • I/O Registers on Input, .

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Revision 11 ProASIC3 nano Flash FPGAs Features and Benefits Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • I/O Registers on Input, Output, and Enable Paths • Selectable Schmitt Trigger Inputs • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate† and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the ProASIC3 Family • Up to Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities and External Feedback • Wide Input Frequency Range (1.5 MHz to 350 MHz) Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Instant On Level 0 Support • Single-Chip Solution • Retains Programmed Design when Powered Off High Performance • 350 MHz System Performance In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)† • FlashLock® Designed to Secure FPGA Contents Clock Conditioning Circuit (CCC) and PLL† Low Power • • • • Low Power ProASIC®3 nano Products 1.5 V Core Voltage for Low Power Support for 1.5 V-Only Systems Low-Impedance Flash Switches Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except ×18 organization)† High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure Enhanced Commercial Temperature Range • –20°C to +70°C Table 1 • ProASIC3 nano Devices ProASIC3 nano Devices ProASIC3 nano-Z System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) RAM Kbits (1,024 bits)2 4,608-Bit Blocks 2 A3PN010 10,000 86 260 – – 1 A3PN0151 A3PN020 A3PN030Z1,2 15,000 128 384 – – 1 – – 4 3 49 – QN68 20,000 172 520 – – 1 – – 4 3 49 52 QN68 30,000 256 768 – – 1 – – 6 2 77 83 QN48, QN68 VQ100 A3PN060 A3PN060Z1 60,000 512 1,536 18 4 1 Yes 1 18 2 71 71 A3PN125 A3PN125Z1 125,000 1,024 3,072 36 8 1 Yes 1 18 2 71 71 A3PN250 A3N250Z1 250,000 2,048 6,144 36 8 1 Yes 1 18 4 68 68 Devices1 FlashROM Kbits Secure (AES) ISP VersaNet Globals I/O Banks Maximum User I/Os (packaged device) Maximum User I/Os (Known Good Die) Package Pins QFN VQFP 2 2 – – 4 2 34 34 QN48 Integrated PLL in CCCs VQ100 VQ100 VQ100 Notes: 1. Not recommended for new designs. 2. A3PN030Z and smaller devices do not support this feature. 3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets. † A3PN030 and smaller devices do not support this feature. January 2013 © 2013 Microsemi Corporation I I/Os Per Package ProASIC3 nano Devices ProASIC3 nano-Z Devices1 Known Good Die QN48 QN68 VQ100 34 34 – – – – 49 – 52 – 49 – A3PN010 A3PN0151 A3PN020 A3PN030Z1 83 34 49 77 A3PN060 A3PN060Z1 71 – – 71 A3PN125 A3PN125Z1 71 – – 71 A3PN250 A3PN250Z1 68 – – 68 Notes: 1. Not recommended for new designs. 2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide to ensure compliance with design and board migration requirements. 3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only. Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions Packages Length × Width (mm\mm) Nominal Area (mm2) Pitch (mm) Height (mm) QN48 6x6 36 0.4 0.90 QN68 8x8 64 0.4 0.90 VQ100 14 x 14 196 0.5 1.20 ProASIC3 nano Device Status ProASIC3 nano Devices A3PN010 A3PN015 A3PN020 A3PN060 A3PN125 A3PN250 Status Production Not recommended for new designs. Production A3PN030Z Production Production Production A3PN060Z A3PN125Z A3PN250Z Not recommended for new designs. Not recommended for new designs. Not recommended for new designs. Not recommended for new designs. ProASIC3 nano-Z Devices Status II R evis i o n 11 ProASIC3 nano Flash FPGAs ProASIC3 nano Ordering Information A3PN250 _ Z 1 VQ G 100 Y I Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial (–40°C to +85°C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead.


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