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Le58QL031DJC Dataheets PDF



Part Number Le58QL031DJC
Manufacturers Legerity
Logo Legerity
Description Quad Low Voltage Subscriber Line Audio-Processing Circuit
Datasheet Le58QL031DJC DatasheetLe58QL031DJC Datasheet (PDF)

™ Le58QL02/021/031 Quad Low Voltage Subscriber Line Audio-Processing Circuit VE580 Series APPLICATIONS „ Codec function on telephone switch line cards ORDERING INFORMATION Device Le58QL02FJC Le58QL021FJC Le58QL021BVC Le58QL031DJC 1. Package (Green)1 44-pin PLCC 44-pin PLCC 44-pin TQFP 32-pin PLCC Tube Tube Tray Tube Packing2 FEATURES „ Low-power, 3.3 V CMOS technology with 5-V tolerant digital inputs „ Software and coefficient compatible to the Le79Q02/ 021/031 QSLAC™ device „ Performs the .

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™ Le58QL02/021/031 Quad Low Voltage Subscriber Line Audio-Processing Circuit VE580 Series APPLICATIONS „ Codec function on telephone switch line cards ORDERING INFORMATION Device Le58QL02FJC Le58QL021FJC Le58QL021BVC Le58QL031DJC 1. Package (Green)1 44-pin PLCC 44-pin PLCC 44-pin TQFP 32-pin PLCC Tube Tube Tray Tube Packing2 FEATURES „ Low-power, 3.3 V CMOS technology with 5-V tolerant digital inputs „ Software and coefficient compatible to the Le79Q02/ 021/031 QSLAC™ device „ Performs the functions of four codec/filters „ Software programmable: — — — — — — — — SLIC device input impedance Transhybrid balance Transmit and receive gains Equalization (frequency response) Digital I/O pins Programmable debouncing on one input Time slot assigner Programmable clock slot and PCM transmit clock edge options The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order. 2. DESCRIPTION The Le58QL02/021/031 Quad Low Voltage Subscriber Line Audio-Processing Circuit (QLSLAC™) devices integrate the key functions of analog line cards into high-performance, veryprogrammable, four-channel codec-filter devices. The QLSLAC devices are based on the proven design of Legerity’s reliable SLAC™ device families. The advanced architecture of the QLSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The QLSLAC devices are software and coefficient compatible to the QSLAC devices. Advanced submicron CMOS technology makes the Le58QL02/ 021/031 QLSLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with four Legerity SLIC devices, a QLSLAC device provides a complete software-configurable solution to the BORSCHT functions. „ Standard microprocessor interface „ A-law, µ-law, or linear coding „ Single or Dual PCM ports available — Up to 128 channels (PCLK at 8.192 MHz) per PCM port — Optional supervision on the PCM highway „ 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or 8.192 MHz master clock derived from MCLK or PCLK „ Built-in test modes with loopback, tone generation, and µP access to PCM data „ Mixed state (analog and digital) impedance scaling „ Performance guaranteed over a 12 dB gain range „ Real Time Data register with interrupt (open drain or TTL output) BLOCK DIAGRAM Analog Dual/Single PCM Highway Signal Processing Channel 1 (CH 1) Signal Processing Channel 2 (CH 2) Signal Processing Channel 3 (CH 3) Signal Processing Channel 4 (CH 4) Time Slot Assigner (TSA) DXA DRA TSCA DXB DRB VIN 3 VOUT 3 VIN 4 VOUT 4 VREF SLIC CD1 1 CD2 1 C31 C41 C51 CD1 2 CD2 2 C32 C42 C52 CD1 3 CD2 3 C33 C43 C53 CD1 4 CD2 4 C34 C44 C54 CHCLK INT CS DIO DCLK Clock & Reference Circuits FS PCLK MCLK/E1 TSCB VIN 1 VOUT 1 VIN 2 VOUT 2 „ Supports multiplexed SLIC device outputs „ Broadcast state „ 256 kHz or 293 kHz chopper clock for Legerity SLIC devices with switching regulator „ Maximum channel bandwidth for V.90 modems RELATED LITERATURE „ 080754 Le58QL061/063 QLSLAC™ Device Data Sheet „ 080761 QSLAC™ to QLSLAC™ Device Design Conversion Guide SLIC Interface (SLI) „ 080758 QSLAC™ to QLSLAC™ Guide to New Designs Microprocessor Interface (MPI) RST Microprocessor Document ID# 080753 Date: Rev: F Version: Distribution: Public Document May 24, 2006 1 Table of Contents APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 BLOCK DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Clock and Reference Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Microproc.


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