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MXL5003S Dataheets PDF



Part Number MXL5003S
Manufacturers MaxLinear
Logo MaxLinear
Description DIGITAL SILICON IC TUNER
Datasheet MXL5003S DatasheetMXL5003S Datasheet (PDF)

MXL5003S DATASHEET REV. 1.0 MAXLINEAR MXL5003S DIGITAL SILICON IC TUNER General Description The MxL5003S is an integrated tuner IC, which meets the specifications of digital (DVB-T, DVBH, ISDB-T 13-seg, ATSC, and 64/256-QAM) TV standards. It enables a manufacturer to design a TV tuner module with a small footprint, low bill-of-materials cost, and low power consumption. The tuner IC can be configured through I2C interface to change modes for receiving different standards. It takes an input from .

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MXL5003S DATASHEET REV. 1.0 MAXLINEAR MXL5003S DIGITAL SILICON IC TUNER General Description The MxL5003S is an integrated tuner IC, which meets the specifications of digital (DVB-T, DVBH, ISDB-T 13-seg, ATSC, and 64/256-QAM) TV standards. It enables a manufacturer to design a TV tuner module with a small footprint, low bill-of-materials cost, and low power consumption. The tuner IC can be configured through I2C interface to change modes for receiving different standards. It takes an input from a 75Ω antenna or cable and produces a programmable channel-selected IF output up to 57MHz. Gain control, LO generation, and channel selectivity functions are completely integrated on the chip, which simplifies board-level design. The nominal power supply is 1.8V. If 1.8V supply is not available, an on-chip regulator can provide the 1.8V supply from a 2.3V to 3.6V supply. The MxL5003S is available in a 6 x 6 mm2 40-pin QFN package. Other package options are available. Features • • • • • • • • • • • • Implemented in CMOS 0.18µm process Tuning range from 44 to 885 MHz Integrated channel filtering requiring no external SAW filters On-chip 75 dB AGC with single AGC ¾ ¾ ¾ ¾ 57 dB RF and 32 dB IF with dual AGC On-chip RSSI with single AGC 165 mA typical ( UHF mode) Flexible support for different demodulator requirements Low power consumption Programmable IF from low to high IF Programmable channel bandwidths from 6, 7, and 8MHz Programmable IF spectrum inversion Clock output available to drive demodulator to save crystal components On-chip regulator voltage input 2.3-3.6V ¾ Can be bypassed with 1.8V supply I2C-compatible digital interface Compatible to additional off-chip LNA to reduce NF, and to increase gain and gain range Applications • High-performance DVB-T, DVB-H, ISDB-T 13-seg, ATSC, and 64/246-QAM television receivers Flat-screen TVs with low power and small form-factor requirements such as LCD monitors Portable applications such as laptops, automobiles, portable DVD players Handheld applications such as cellular phones and PDAs Pin Configuration • • • July 20, 2006 Confidential Page 1 of 13 MXL5003S DATASHEET REV. 1.0 IC Block Diagram The proprietary architecture of the tuner is illustrated in the functional block diagram of Fig. 1. The chip utilizes a proprietary architecture, which achieves the required channel selection using a multistage channel filter. The RF input is first mixed to a fixed frequency, then after channel filtering it is mixed to a programmable IF frequency. Anti-alias filtering after 2nd mixing stage removes any out-ofband harmonics. A tunable IF LO allows for programmable IF frequencies. Automatic gain control is distributed throughout the signal path for optimum noise and linearity performance. In single-AGC mode, VAGC_RF controls both the RF and IF gain. An RSSI block can be enabled to detect the LNA output and automatically adjusts the gain of the LNA. In dual-AGC mode, VAGC_RF and VAGC_IF control the RF and IF gain. .


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