NE33200

SUPER LOW NOISE HJ FET NE33200 FEATURES VERY LOW NOISE FIGURE: 0.75 dB typical at 12 GHz Optimum Noise Figure, NFOPT (dB) 4 3.5 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA 24 21 18 15 12 9 6 NF 0.5 0 1 10 30 3 0 HIGH ASSOCIATED GAIN: 10.5 dB Typical at 12 GHz GATE LENGTH: 0.3 µm GATE WIDTH: 280 µm 3 2.5 2 1.5 1 DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create a two-dimensional electron gas layer with very high electron mobility. Its excellent low noise figure and high associated gain make it suitable for commercial and industrial applications. NEC's stringent quality assurance and test procedures assure the highest reliability and performance. Frequency, f (GHz) ELECTRICAL CHARACTERISTICS (TA = 25°C) PART NUMBER PACKAGE OUTLINE SYMBOLS NFOPT1 PARAMETERS AND CONDITIONS Noise Figure, VDS = 2 V, ID = 10 mA, f = 4 GHz f = 12 GHz Associated Gain, VDS = 2 V, ID = 10 mA, f = 4 GHz f = 12 GHz Output Power at 1 dB Gain Compression Point, f = 12 GHz VDS = 2 V, IDS = 10 mA VDS = 2 V, IDS = 20 mA Gain at P1dB, f = 12 GHz VDS = 2 V, IDS = 10 mA VDS = 2 V, IDS = 20 mA Saturated Drain Current, VDS = 2 V, VGS = 0 V Pinch-off Voltage, VDS = 2 V, ID = 100 µA Transconductance, VDS = 2 V, ID = 10 mA Gate to Source Leakage Current, VGS = -5 V Thermal Resistance (Channel to Case) UNITS dB dB dB dB dBm dBm dB dB mA V mS µA °C/W 15 -2.0 45 MIN NE33200 00 (Chip) TYP 0.35 0.7...