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BUK9209-40B Dataheets PDF



Part Number BUK9209-40B
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description TrenchMOS logic level FET
Datasheet BUK9209-40B DatasheetBUK9209-40B Datasheet (PDF)

BUK9209-40B TrenchMOS™ logic level FET M3D300 Rev. 02 — 12 December 2003 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS™ technology. 1.2 Features s Very low on-state resistance s 185 °C rated s Q101 compliant s Logic level compatible. 1.3 Applications s Automotive systems s Motors, lamps and solenoids s 12 V loads s General purpose power switching. 1.4 Quic.

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BUK9209-40B TrenchMOS™ logic level FET M3D300 Rev. 02 — 12 December 2003 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS™ technology. 1.2 Features s Very low on-state resistance s 185 °C rated s Q101 compliant s Logic level compatible. 1.3 Applications s Automotive systems s Motors, lamps and solenoids s 12 V loads s General purpose power switching. 1.4 Quick reference data s EDS(AL)S ≤ 242 mJ s ID ≤ 75 A s RDSon = 7.6 mΩ (typ) s Ptot ≤ 167 W. 2. Pinning information Table 1: Pin 1 2 3 mb Pinning - SOT428 (D-PAK), simplified outline and symbol Simplified outline [1] Description gate (g) drain (d) source (s) mounting base; connected to drain (d) Symbol d mb g s MBB076 2 1 Top view 3 MBK091 SOT428 (D-PAK) [1] It is not possible to make connection to pin 2 of the SOT428 package. Philips Semiconductors BUK9209-40B TrenchMOS™ logic level FET 3. Ordering information Table 2: Ordering information Package Name BUK9209-40B D-PAK Description Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped). Version SOT428 Type number 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDS VDGR VGS ID Parameter drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 IDM Ptot Tstg Tj IDR IDRM EDS(AL)S peak drain current total power dissipation storage temperature junction temperature reverse drain current (DC) peak reverse drain current non-repetitive drain-source avalanche energy Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 75 A; VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω; starting Tj = 25 °C [1] [2] [1] [2] [1] Conditions RGS = 20 kΩ Min −55 −55 - Max 40 40 ±15 99 75 70 396 167 +185 +185 99 75 396 242 Unit V V V A A A A W °C °C A A A mJ Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Source-drain diode Avalanche ruggedness [1] [2] Current is limited by power dissipation chip rating. Continuous current is limited by package. 9397 750 12234 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 02 — 12 December 2003 2 of 12 Philips Semiconductors BUK9209-40B TrenchMOS™ logic level FET 120 Pder (%) 80 03no96 100 ID (A) 75 03no60 Capped at 75A due to package 50 40 25 0 0 50 100 150 200 Tmb (°C) 0 0 50 100 150 200 Tmb (°C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) VGS ≥ 5 V Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Continuous drain current as a function of mounting base temperature. 103 03no59 ID (A) Limit RDSon = VDS / ID tp = 10 µ s 102 100 µ s Capped at 75 A due to package 1 ms 10 DC 10 ms 100 ms 1 1 10 VDS (V) 102 Tmb = 25 °C; IDM single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 12234 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 02 — 12 December 2003 3 of 12 Philips Semiconductors BUK9209-40B TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Symbol Rth(j-a) Rth(j-mb) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to mounting base Figure 4 Conditions Min Typ 71.4 Max 0.95 Unit K/W K/W 5.1 Transient thermal impedance 1 δ = 0.5 Zth(j-mb) (K/W) 03nk52 0.2 0.1 0.05 0.02 10-1 10-2 P single shot δ= tp T tp T 10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) t 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 12234 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 02 — 12 December 2003 4 of 12 Philips Semiconductors BUK9209-40B TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 0.25 mA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 185 °C Tj = −55 °C IDSS drain-source leakage current VDS = 40 V; VGS = 0 V Tj = 25 °C Tj = 185 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = 185 °C VGS = 4.5 V; ID = 25 A VGS = 10 V; ID = 25 A Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf Ld Ls total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance internal source inductance measured from drain to center of die measured from source lead .


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