Document
LatticeXP2™ Family Data Sheet
DS1009 Version 2.2, September 2014
LatticeXP2 Family Data Sheet Introduction
February 2012
Features
flexiFLASH™ Architecture
• Instant-on • Infinitely reconfigurable • Single chip • FlashBAK™ technology • Serial TAG memory • Design security
Live Update Technology
• TransFR™ technology • Secure updates with 128 bit AES encryption • Dual-boot with external SPI
sysDSP™ Block
• Three to eight blocks for high performance Multiply and Accumulate
• 12 to 32 18x18 multipliers • Each block supports one 36x36 multiplier or four
18x18 or eight 9x9 multipliers
Embedded and Distributed Memory
• Up to 885 Kbits sysMEM™ EBR • Up to 83 Kbits Distributed RAM
sysCLOCK™ PLLs
• Up to four analog PLLs per device • Clock multiply, divide and phase shifting
Data Sheet DS1009
Flexible I/O Buffer
• sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II – HSTL15 class I; HSTL18 class I, II – PCI – LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
Pre-engineered Source Synchronous Interfaces
• DDR / DDR2 interfaces up to 200 MHz • 7:1 LVDS interfaces support display applications • XGMII
Density And Package Options
• 5k to 40k LUT4s, 86 to 540 I/Os • csBGA, TQFP, PQFP, ftBGA and fpBGA packages • Density migration supported
Flexible Device Configuration
• SPI (master and slave) Boot Flash Interface • Dual Boot Image supported • Soft Error Detect (SED) macro embedded
System Level Support
• IEEE 1149.1 and IEEE 1532 Compliant • On-chip oscillator for initialization & general use • Devices operate with 1.2V power supply
Table 1-1. LatticeXP2 Family Selection Guide
Device LUTs (K) Distributed RAM (KBits) EBR SRAM (KBits) EBR SRAM Blocks sysDSP Blocks 18 x 18 Multipliers VCC Voltage GPLL Max Available I/O Packages and I/O Combinations 132-Ball csBGA (8 x 8 mm) 144-Pin TQFP (20 x 20 mm) 208-Pin PQFP (28 x 28 mm) 256-Ball ftBGA (17 x17 mm) 484-Ball fpBGA (23 x 23 mm) 672-Ball fpBGA (27 x 27 mm)
XP2-5 5 10
166 9 3 12 1.2 2
172
86 100 146 172
XP2-8 8 18
221 12 4 16 1.2 2 201
86 100 146 201
XP2-17 17 35 276 15 5 20 1.2 4 358
XP2-30 29 56 387 21 7 28 1.2 4 472
XP2-40 40 83 885 48 8 32 1.2 4 540
146 201 201 358 363 363
472 540
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1-1 DS1009 Introduction_01.4
Introduction LatticeXP2 Family Data Sheet
Introduction
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live .