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HCTS08MS Dataheets PDF



Part Number HCTS08MS
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description Radiation Hardened Quad 2-Input AND Gate
Datasheet HCTS08MS DatasheetHCTS08MS Datasheet (PDF)

HCTS08MS August 1995 Radiation Hardened Quad 2-Input AND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14 TOP VIEW A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD(Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Survivability: >1 x • Dose Rate Upset >10 10 1012 Rads (Si)/.

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HCTS08MS August 1995 Radiation Hardened Quad 2-Input AND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14 TOP VIEW A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD(Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Survivability: >1 x • Dose Rate Upset >10 10 1012 Rads (Si)/Sec RAD(Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V - VIH = VCC/2 • Input Current Levels Ii ≤ 5µA at VOL, VOH A1 B1 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3 Description The Intersil HCTS08MS is a Radiation Hardened Quad 2-Input AND Gate. A high on both inputs force the output to a High state. The HCTS08MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS08MS is supplied in a 14 lead Ceramic Flatpack Package (K suffix) or a 14 lead SBDIP Package (D suffix). Y1 A2 B2 Y2 GND TRUTH TABLE INPUTS An Bn L H L H OUTPUTS Yn L L L H Ordering Information PART NUMBER HCTS08DMSR TEMPERATURE RANGE -55oC to +125oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample PACKAGE 14 Lead SBDIP L L H H NOTE: L = Logic Level Low, H = Logic level High 14 Lead Ceramic Flatpack 14 Lead SBDIP HCTS08KMSR -55oC to +125oC Functional Diagram (1, 4, 9, 12) An (3, 6, 8, 11) Yn (2, 5, 10, 13) Bn HCTS08D/ Sample HCTS08K/ Sample HCTS08HMSR +25oC +25oC Sample 14 Lead Ceramic Flatpack Die +25oC Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Spec Number File Number 1 518842 2136.2 DB NA Specifications HCTS08MS Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output . . . . . . . . . . . . . . . . . . . . . . .±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Reliability Information Thermal Resistance θJA θJC SBDIP Package . . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W Maximum Package Power Dissipation at +125oC SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.66W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. Operating Conditions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V 1 2, 3 Output Current (Source) IOH VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V VCC = 4.5V, VIH = 2.25V, IOL = 50µA, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOL = 50µA, VIL = 0.8V Output Voltage High VOH VCC = 4.5V, VIH = 2.25V, IOH = -50µA, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOH = -50µA, VIL = 0.8V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC.


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