IDT8P34S1208I

1:8 LVDS Output 1.8V Fanout Buffer IDT8P34S1208I DATA SHEET General Description The IDT8P34S1208I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8P34S1208I is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8P34S1208I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Features Eight low skew, low additive jitter LVDS output pairs Two selectable, differential clock input pairs Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML Maximum input clock frequency: 1.2GHz (maximum) LVCMOS/LVTTL interface levels for the control input select pin Output skew: 20ps (typical) Propagation delay: 315ps (typical) Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 41fs (typical) Full 1.8V supply voltage Lead-free (RoHS 6), 28-Lead VFQFN packaging -40°C to 85°C ambient operating temperature Block Diagram. Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Pin Assignment 21 20 19 18 17 1...