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A32100DX Dataheets PDF



Part Number A32100DX
Manufacturers Actel
Logo Actel
Description HiRel FPGAs
Datasheet A32100DX DatasheetA32100DX Datasheet (PDF)

v3.0 HiRel FPGAs Fe a t ur es • Low-Power 0.8µ CMOS Technology 32 0 0D X Fe a t ur es • Highly Predictable Performance with 100% Automatic Placement and Routing • Device Sizes from 1,200 to 20,000 Gates • Up to 6 Fast, Low-Skew Clock Networks • Up to 202 User-Programmable I/O Pins • • • • • • • • • More Than 500 Macro Functions Up to 1,276 Dedicated Flip-Flops I/O Drive to 10 mA Devices Available to DSCC SMD CQFP and CPGA Packaging Nonvolatile, User Programmable Logic Fully Tested Prior to Sh.

  A32100DX   A32100DX


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v3.0 HiRel FPGAs Fe a t ur es • Low-Power 0.8µ CMOS Technology 32 0 0D X Fe a t ur es • Highly Predictable Performance with 100% Automatic Placement and Routing • Device Sizes from 1,200 to 20,000 Gates • Up to 6 Fast, Low-Skew Clock Networks • Up to 202 User-Programmable I/O Pins • • • • • • • • • More Than 500 Macro Functions Up to 1,276 Dedicated Flip-Flops I/O Drive to 10 mA Devices Available to DSCC SMD CQFP and CPGA Packaging Nonvolatile, User Programmable Logic Fully Tested Prior to Shipment 100% Military Temperature Tested (–55°C to +125°C) QML Certified Devices • 100 MHz System Logic Integration • Highest Speed FPGA SRAM, up to 2.5 kbits Configurable Dual-Port SRAM • Fast Wide-Decode Circuitry • Low-Power 0.6µ CMOS Technology 12 0 0X L Fe at ure s • Pin for Pin Compatible with ACT 2 • System Performance to 50 MHz over Military Temperature • Low-Power 0.6µ CMOS Technology A CT 2 Fe at ure s • Proven Reliability Data Available • Successful Military/Avionics Supplier for Over 10 Years A CT 3 Fe at ure s • Best-Value, High-Capacity FPGA Family • System Performance to 40 MHz over Military Temperature • Low-Power 1.0µ CMOS Technology A CT 1 Fe at ure s • Highest-Performance, Highest-Capacity FPGA Family • System Performance to 60 MHz over Military Temperature • Lowest-Cost FPGA Family • System Performance to 20 MHz over Military Temperature • Low-Power 1.0µ CMOS Technology Pr od uc t F am i l y P r o f i l e (more devices on page 2) Family Device Capacity System Gates Logic Gates SRAM Bits Logic Modules S-Modules C-Modules Decode Flip-Flops (Maximum) User I/Os (Maximum) Performance System Speed (maximum) Packages (by Pin Count) CPGA CQFP 3200DX A32100DX 15,000 10,000 2,048 1,362 700 662 20 738 152 55 MHz A32200DX 30,000 20,000 2,560 2,414 1,230 1,184 24 1,276 202 55 MHz A1425A 3,750 2,500 NA 310 160 150 NA 435 100 60 MHz 133 132 ACT 3 A1460A 9,000 6,000 NA 848 432 416 NA 976 168 60 MHz 207 196 A14100A 15,000 10,000 NA 1,377 697 680 NA 1,493 228 60 MHz 257 256 1200XL A1280XL 12,000 8,000 1,232 624 608 NA 998 140 50 MHz 176 172 84 208, 256 J an u a r y 2 0 0 0 1 © 2000 Actel Corporation Pr od uc t F am i l y P r o f i l e Family Device Capacity System Gates Logic Gates SRAM Bits Logic Modules S-Modules C-Modules Decode Flip-Flops (maximum) User I/Os (maximum) Packages (by pin count) CPGA CQFP Performance System Speed (maximum) ACT 2 A1240A 6,000 4,000 NA 684 348 336 NA 568 104 132 — 40 MHz A1280A 12,000 8,000 NA 1,232 624 608 NA 998 140 176 172 40 MHz ACT 1 A1010B 1,800 1,200 NA 295 — 295 NA 147 57 84 — A1020B 3,000 2,000 NA 547 — 547 NA 273 69 84 84 20 MHz 20 MHz H i gh - R el i a bi l i t y , L o w - Ri s k So l ut i on Actel builds the most reliable field programmable gate arrays (FPGAs) in the industry, with overall antifuse reliability ratings of less than 10 Failures-In-Time (FITs), corresponding to a useful life of more than 40 years. Actel FPGAs have been production proven, with more than five million devices shipped and more than one trillion antifuses manufactured. Actel devices are fully tested prior to shipment, with an outgoing defect level of less than 100 ppm. (Further reliability data is available in the Actel Device Reliability Report, at http://www.actel.com/hirel). B en ef i t s Mi nim i zed C os t Ri sk junction temperatures. Actel’s non-PLD architecture delivers lower dynamic operating current. Our reliability tests show a very low failure rate of 6.6 FITs at 90°C junction temperature with no degradation in AC performance. Special stress testing at wafer test eliminates infant mortalities prior to packaging. M ini m ized S ecu ri ty R is k Reverse engineering of programmed Actel devices from optical or electrical data is extremely difficult. Programmed antifuses cannot be identified from a photograph or by using an SEM. The antifuse map cannot be deciphered either electrically or by microprobing. Each device has a silicon signature that identifies its origins, down to the wafer lot and fabrication facility. M ini m ized T es ti ng Ri sk With Actel’s line of development tools, designers can produce as many chips as they choose for just the cost of the device itself. There will be no NRE charges to cut into the development budget each time a new design is tried. M i n im i z e d T i m e R is k After the design is entered, placement and routing is automatic, and programming the device takes only about 5 to 15 minutes for an average design. Designers save time in the design entry process by using tools with which they are familiar. Mi nim i zed R el iabi li ty R is k Unprogrammed Actel parts are extensively tested at the factory. Routing tracks, logic modules, and programming, debug and test circuits are 100 percent tested before shipment. AC performance is ensured by special speed path tests, and programming circuitry is verified on test antifuses. During the programming process, an algorithm is run to ensure that all antifuses are correctly programmed. In additio.


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