HCTS75MS

HCTS75MS September 1995 Radiation Hardened Dual 2-Bit Bistable Transparent Latch Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW Q0 1 D0 1 D1 1 E 2 VCC D0 2 D1 2 Q1 2 1 2 3 4 5 6 7 8 16 1 Q0 15 1 Q1 14 1 Q1 13 1 E 12 11 GND 2 Q0 Features 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min Input Current Levels Ii ≤ 5µA at VOL, VOH 10 2 Q0 9 2 Q1 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW Q0 1 D0 1 D1 1 E 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 Q0 1 Q1 1 Q1 1 E GND 2 Q0 2 Q0 2 Q1 Description The Intersil HCTS75MS is a Radiation Hardened dual 2-bit bistable transparent latch. Each of the two latches are controlled by a separate enable input (E) which are active low. E low latches the output state. The HCTS75MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS75MS is supplied in a 16 le...