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HD-15530
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15530 is a high performance CMOS device intended to service the requirements of MlL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate completely independent of each other, except for the Master Reset functions. This circuit meets many of the requirements of MIL-STD1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. This integrated circuit is fully guaranteed to support the 1MHz data rate of MlL-STD-1553 over both temperature and voltage. It interfaces with CMOS, TTL or N channel support circuitry, and uses a standard 5V supply. The HD-15530 can also be used in many party line digital data communications applications, such as an environmental control system driven from a single twisted pair cable of fiber optic cable throughout the building.
March 1997
Features
• Support of MlL-STD-1553 • Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s • Sync Identification and Lock-In • Clock Recovery • Manchester II Encode, Decode • Separate Encode and Decode • Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE CERDIP TEMP. RANGE -40oC to +85oC -55oC to +125oC SMD# CLCC -40oC to +85oC -55oC to +125oC SMD# PDIP -40oC to +85oC 1.25 MEGABIT/s HD1-15530-9 HD1-15530-8 7802901JA HD4-15530-9 HD4-15530-8 78029013A HD3-15530-9 E24.6 J28.A PKG. NO. F24.6
Pinouts
HD-15530 (CERDIP, PDIP) TOP VIEW
SERIAL DATA OUT VALID WORD 1 ENCODER SHIFT CLK 2 TAKE DATA 3 SERIAL DATA OUT 4 DECODER CLK 5 24 VCC 23 ENCODER CLK 22 SEND CLK IN 21 SEND DATA 20 SYNC SELECT 19 ENCODER ENABLE 18 SERIAL DATA IN 17 BIPOLAR ONE OUT 16 OUTPUT INHIBIT BIPOLAR 15 ZERO OUT 14 ÷ 6 OUT 13 MASTER RESET NC BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK 7 8 9 10 11 12 COMMAND/ DATA SYNC 13 DECODER RESET 14 GND 15 MASTER RESET 16 17 BIPOLAR ZERO OUT 18 OUTPUT INHIBIT 23 22 21 20 19 NC SYNC SELECT ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT DECODER CLK NC 5 6
HD-15530 (CLCC) TOP VIEW
TAKE DATA ENCODER SHIFT CLK ENCODER CLK SEND CLK IN 27 26 25 24 SEND DATA NC
VALID WORD 1
4
3
2
BIPOLAR ZERO IN 6 BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8 DECODER SHIFT CLK 9 COMMAND/ DATA SYNC 10 DECODER RESET 11 GND 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
÷ 6 OUT
VCC 28
FN2960.1
142
HD-15530 Block Diagrams
ENCODER
12 13 22 14 GND MASTER RESET SEND CLK IN VCC OUTPUT INHIBIT 24 UNIPOLAR 8 DATA IN BIPOLAR 7 ONE IN BIPOLAR 6 ZERO IN
DECODER
3 TRANSITION FINDER CHARACTER IDENTIFIER TAKE DATA
÷ 6 OUT ÷6
ENCODER CLK BIT COUNTER
÷2
17 CHARACTER FORMER 15
16 BIPOLAR ONE OUT BIPOLAR ZERO OUT
10 COMMAND/ DATA SYNC 4 SERIAL DATA OUT
23
DECODER CLK 18 19 20 SYNC SELECT MASTER RESET
5
SYNCHRONIZER
BIT RATE CLK
PARITY 1 VALID CHECK WORD 9 DECODER SHIFT CLK
13 DECODER RESET 11 BIT COUNTER
21
2
SEND DATA
SERIAL DATA IN
ENCODER ENABLE ENCODER SHIFT CLK
Pin Description
PIN NUMBER 1 2 3 4 5 TYPE O O O O I NAME VALID WORD ENCODER SHIFT CLOCK TAKE DATA SERIAL DATA OUT DECODER CLOCK SECTION Decoder Encoder Decoder Decoder Decoder DESCRIPTION Output high indicates receipt of a valid word, (valid parity and no Manchester errors). Output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of Encoder Shift Clock. Output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. Delivers received data in correct NRZ format. Input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder, input a frequency equal to 12X the data rate. A high input should be applied when the bus is in its negative state. This pin must be held high when the Unipolar input is used. A high input should be applied when the bus is in its positive state. This pin must be held low when the Unipolar input is used. With pin 6 high and pin 7 low, this pin enters unipolar data into the transition finder circuit. If not used this input must be held low. Output which delivers a frequency (DECODER CLOCK ÷ 12), synchronized by the recovered serial data stream. Output of a high from this pin occurs during output of decoded data which was preceded by a Command (or Status) synchronizing character. A low output indicates a Data synchronizing character. A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. G.