Document
P-Channel Enhancement Mode MOSFET
Product Summary
VDS (V) ID (A)
RDS(ON) (mΩ) Max 25 @VGS = -10V -30V -30A 45 @VGS = -5V 55 @VGS = -4.5V
G S D
SSD3030P
TO-252
D
FEATURES
Super high density cell design for low RDS(ON) . Rugged and reliable. TO-252 package. Pb free.
G S
ABSOLUTE MAXIMUM RATINGS (TA = 25 C unless otherwise noted)
Parameter
Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous @ TJ = 125 C -Pulsed
b o
o
Symbol
VDS VGS ID IDM
a
Limit
-30 + - 25 -30 -60 -1.7 50 -55 to 150
Unit
V V A A A W
o
Drain-Source Diode Forward Current Maximum Power Dissipation
a
IS PD TJ, TSTG
Operating Junction and Storage Temperature Range
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient
a
R R
JC JA
3 50
o
C/W
South Sea Semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. South Sea Semiconductor, January 2008 (Rev 2.1)
1
SSD3030P
P-Channel Electrical Characteristics (TA = 25 C unless otherwise noted)
Parameter
Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage Gate Threshold Voltage
o
Symbol
BVDSS IDSS IGSS VGS(th)
Condition
VGS=0V, ID=-250 A
Min
-30
Typ
c
Max
Unit
V
VDS=-24V, VGS=0V VGS= 25V, VDS=0V A -1 -1.9
-1 100 -2.5 25 45 55 -40 15 1000 200 110 17.6 17.4 169 95.4 20 11 3.5 6 -0.75 -1.2 25 150 1200
A nA V m
VDS=VGS ID=-250 VGS=-10V, ID=-20A
Drain-Source On-State Resistance
RDS(ON)
VGS= - 5V, ID = -10A VGS=-4.5V, ID=-10A
On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Diode Forward Voltage
ID(ON) gFS CISS COSS CRSS tD(ON) tr tD(OFF) tf Qg Qgs Qgd VSD
VDS=-5V, VGS=-10V VDS=-5V, ID=-5.3A VDS=-15V VGS=0V f=1.0MHz VDD=-15V, ID=-1A, VGEN=-10V, RGEN=6 ,
A S
PF
ns
VDS=-15V, ID= - 8A, VGS = -10V VDS=-15V, ID= - 8A, VGS = -4.5V
VDS= -15V, ID= -6A, VGS= -10V VGS=0V, ID= -1A
nC
V
Notes a. Surface Mounted on FR4 Board, t <10 - sec. b. Pulse Test Pulse Width < 300 s, Duty Cycle < - 2%. c. Guaranteed by design, not subject to production testing.
South Sea Semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. South Sea Semiconductor, January 2008 (Rev 2.1)
2
SSD3030P
10 8 -VGS = 4V 25 Tj = 125 C
o
25 C
o
-55 C
o
-ID, Drain Current (A)
-VGS = 10, 9, 8, 7, 6, 5V 6
-ID, Drain Current (A)
-VGS = 3V
20
15
4
10
2
5
0 0 2 4 6 8 10 12
0 0 0.6 1.0 1.4 1.8 2.2 2.6
-VDS, Drain-to-Source Voltage (V)
-VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
1200
Figure 2. Transfer Characteristics
1.8 VGS = -10V ID = -8A
Ciss
800 600 400 200 0 0 5
RDS(ON), On-Resistance Normalized ( )
30
1000
C, Capacitance (pF)
1.6 1.4 1.2 1.0 0.8 0.6
Coss
Crss
10 15 20 25
-55
-25
0
25
50
75
100
125
-VDS, Drain-to-Source Voltage (V)
Tj, Junction Tempertature ( O C)
Figure 3. Capacitance
1.3
Figure 4. On-Resistance Variation with Temperature
BVDSS, Normalized Drain-Source Breakdown Voltage
1.15 ID = -250 A 1.10 1.05 1.00 0.95 0.90 0.85 -50 -25 0 25 50 75 100
o
Vth, Normalized Gate-Source Threshold Voltage
1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50
VDS = VGS ID = -250 A
Tj, Junction Temperature ( C)
o
-25
0
25
50
75
100
125
125
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation with Temperature
Figure 6. Breakdown Voltage Variation with Temperature
South Sea Semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. South Sea Semiconductor, January 2008 (Rev 2.1)
3
SSD3030P
20 20.0
-IS, Source-Drain Current (A)
gFS, Transconductance (S)
VGS = 0V 10.0
16
12
8
4 VDS = -15V 0 0 5 10 15 20
1.0 0.2 0.4 0.6 0.8 1.0 1.2
-IDS, Drain-Source Current (A)
-VSD, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation with Drain Current
10
Figure 8. Body Diode Forward Voltage Variation with Source Current
100
100µs 1ms
-VGS, Gate to Source Voltage (V)
-ID, Drain Current (A)
8
VDS = -15V ID = -8A
10
RDS(ON) LIMIT
10ms
6
1
VGS = 10V SINGLE PULSE RθJA = 96oC/W TA = 25oC
DC
1 10s
100ms
4 2
0.1
0 0 3
0.01
Qg, Total Gate Charge (nC)
6
9
12
15
18
21
24
0.01
0.10
1.00
-VSD, Drain-to-Source Voltage (V)
10.00
100.00
Figure 9. Gate Charge
Figure 10. Maximum Safe Operating Area
South Sea Semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. South Sea Semiconductor, January 2008 (Rev 2.1)
4
SSD3030P
VDD VIN VGS RGEN G S
VIN
50% 10% 50%
ton td(on) tr
90%
toff td(off)
90% 10%
RL D VOUT
tf
VOUT
10%
90%
INVERTED PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
1
D = 0.5
r(t), Normalized Effective Transient Thermal Impedance
0.2
0.1
0.1 0.05 0.02
RθJA(t) = r(t) * R.