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AT91SAM9G46 Dataheets PDF



Part Number AT91SAM9G46
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description AT91 ARM Thumb-based Microcontrollers
Datasheet AT91SAM9G46 DatasheetAT91SAM9G46 Datasheet (PDF)

Features • 400 MHz ARM926EJ-S™ ARM® Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories – 4-port, 4-bank DDR2/LPDDR Controller – External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface – One 64-KByte internal ROM, embedding bootstrap routine Peripherals – LCD Controller supporting STN and TFT .

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Features • 400 MHz ARM926EJ-S™ ARM® Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories – 4-port, 4-bank DDR2/LPDDR Controller – External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface – One 64-KByte internal ROM, embedding bootstrap routine Peripherals – LCD Controller supporting STN and TFT displays up to 1280*860 – ITU-R BT. 601/656 Image Sensor Interface – Dual High Speed USB Host and a High Speed USB Device with On-Chip Transceivers – 10/100 Mbps Ethernet MAC Controller – Two High Speed Memory Card Hosts (SDIO, SDCard, e.MMC and CE ATA) – AC'97 controller – Two Master/Slave Serial Peripheral Interfaces – Two Three-channel 16-bit Timer/Counters – Two Synchronous Serial Controllers (I2S mode) – Four-channel 16-bit PWM Controller – Two Two-wire Interfaces – Four USARTs with ISO7816, IrDA, Manchester and SPI modes – 8-channel 10-bit ADC with 4-wire Touch Screen support Cryptography – TRNG True Random Number Generator – AES256-, 192-, 128-bit Key Algorithm, – TDES Compliant with FIPS PUB 46-3 Specifications – SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2 System – 133 MHz twelve 32-bit layer AHB Bus Matrix – 39 DMA Channels – Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash – Reset Controller with on-chip Power-on Reset – Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators – Internal Low-power 32 kHz RC Oscillator – One PLL for the system and one 480 MHz PLL optimized for USB High Speed – Two Programmable External Clock Signals – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock I/O – Five 32-bit Parallel Input/Output Controllers – 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input Package – 324-ball TFBGA, pitch 0.8 mm • AT91 ARM Thumb-based Microcontrollers AT91SAM9G46 Preliminary Summary • • • • NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. 11028BS–ATARM–26-Apr-10 1. Description The ARM926EJ-S based AT91SAM9G46 features the frequently requested combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400MHz and multiple 100+ Mbps data rate peripherals, the AT91SAM9G46 has the performance and bandwidth to the network or local storage media to provide an adequate user experience. The AT91SAM9G46 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 39 DMA channels, a dual external bus interface and distributed memory including a 64KByte SRAM that can be configured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor and the high speed peripherals. On-chip hardware accelerators with DMA support enable high-speed data encryption and authentication of the transferred data or application. Supported standards are up to 256-bit AES, FIPS PUB 46-3 compliant TDES and FIPS Publication 180-2 compliant SHA1 and SHA256. A True Random Number Generator is embedded for key generation and exchange protocols. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing. The AT91SAM9G46 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. 2 AT91SAM9G46 11028BS–ATARM–26-Apr-10 Figure 2-1. EL NT RS T TD I TD O TM TCS K RT CK JTA GS BM 2. Block Diagram TST In-Circuit Emulator PA LCD EMAC 8-CH DMA ISI HS EHCI USB HOST DMA DMA DMA DMA DMA HS USB PB System Controller JTAG / Boundary Scan PIO HS Transceiver PCK0-PCK1 FIQ IRQ AIC ARM926EJ-S PIO DBGU H F S HH DPA SD ,H PA FS D , H HS MA V DM B G A DF S D DP H SD /HFS P/H DP HS B,D LC D F P D B,D SDM LC D0 HS /H D -L DM FS LC VSY CDD D D / N 2 H HSMB LD DO C,L 3 T DM D C LC EN CK DH B SY DP ,LC NC W D IS R, CC I_ IS DO- LCD I_ IS M IS PCK I_D OD I_ 11 I H S I_ SY IS VS NC I _M YN C C ET K X ET CK X E EC EN RX R -E C ER S-E TX K E ER XER COL R X ET 0-E ERX X R D E 0-ET X3 V M EM DC X3 DI O HS Transceiver M C I M 0_D CI 0_ A0M C M DA CI0 C ,M _ M I0_ CI DA C 7 C 1 I 1_ K, _C DA MC DA 0- I1_ M CI CK 1_ DA TW 7 TW D0 C -T K 0- WD C TW 1 T C S RT 0- K1 S CT S 0-R S3 C K T RD 0-S S3 X C TX 0-R K3 D D 0 X PW -TX 3 D3 M 0PW TC M L 3 K T 0 I O -TC A0 L TI -TI K2 O O TC B0 A2 L -T TI K3 IO B O TI .


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