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MX25L1025C Dataheets PDF



Part Number MX25L1025C
Manufacturers Macronix International
Logo Macronix International
Description 1M-BIT [x 1] CMOS SERIAL FLASH
Datasheet MX25L1025C DatasheetMX25L1025C Datasheet (PDF)

MX25L1025C 1M-BIT [x 1] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 1,048,576 x 1 bit structure • 32 Equal Sectors with 4K byte each - Any Sector can be erased individually • 2 Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast access time: 8.

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MX25L1025C 1M-BIT [x 1] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 1,048,576 x 1 bit structure • 32 Equal Sectors with 4K byte each - Any Sector can be erased individually • 2 Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast access time: 85MHz serial clock and 66MHz serial clock - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block) • Low Power Consumption - Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz - Low active programming current: 15mA (max.) - Low active erase current: 15mA (max.) - Low standby current: 10uA (max.) - Deep power-down mode 1uA (typical) • Minimum 100,000 erase/program cycles SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Block Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions. • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI Input - Serial Data Input • SO Output P/N: PM1480 1 REV. 1.1, JUL. 21, 2009 MX25L1025C • • • - Serial Data Output WP# pin - Hardware write protection HOLD# pin - pause the chip without diselecting the chip PACKAGE - 8-pin SOP (150mil) - All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX25L1025C is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The MX25L1025C feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. The MX25L1025C provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L1025C utilize Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. P/N: PM1480 2 REV. 1.1, JUL. 21, 2009 MX25L1025C PIN CONFIGURATIONS 8-PIN SOP (150mil) CS# SO WP# GND 1 2 3 4 8 7 6 5 VCC HOLD# SCLK SI PIN DESCRIPTION SYMBOL CS# SI SO SCLK HOLD# VCC GND WP# DESCRIPTION Chip Select Serial Data Input Serial Data Output Clock Input Hold, to pause the device without deselecting the device + 3.3V Power Supply Ground Write Protection P/N: PM1480 3 REV. 1.1, JUL. 21, 2009 MX25L1025C BLOCK DIAGRAM Address Generator X-Decoder Memory Array Page Buffer SI Data Register Y-Decoder SRAM Buffer Mode Logic State Machine Sense Amplifier HV Generator CS# Output Buffer SO SCLK Clock Generator P/N: PM1480 4 REV. 1.1, JUL. 21, 2009 MX25L1025C DATA PROTECTION The MX25L1025C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion .


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