Document
MX29GL320E T/B MX29GL320E H/L
MX29GL320E T/B, MX29GL320E H/L DATASHEET
P/N:PM1509
REV. 1.0, OCT. 12, 2009
1
MX29GL320E T/B MX29GL320E H/L
FEATURES
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
GENERAL FEATURES • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations - V I/O voltage must tight with VCC - VI/O=VCC=2.7V~3.6V • Byte/Word mode switchable - 4,194,304 x 8 / 2,097,152 x 16 • Sector architecture - MX29GL320E T/B: 63 x 32Kword(64KB) + 8 x 4Kword(8KB) boot sector - MX29GL320E H/L: 64 x 32Kword(64KB) Uniform sector • 16-byte/8-word page read buffer • 32-byte/16-word write buffer • Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable • Advanced sector protection function (Persifent and Password Protect) • Latch-up protected to 100mA from -1V to 1.5xVcc • Low Vcc write inhibit : Vcc ≤ VLKO • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Deep power down mode PERFORMANCE • High Performance - Fast access time: 70ns - Page access time: 25ns - Fast program time: 11us/word - Fast erase time: 0.6s/sector • Low Power Consumption - Low active read current: 30mA (typical) at 5MHz - Low standby current: 30uA (typical) • Typical 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Program/Erase Suspend & Program/Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased - Suspends sector program operation to read data from another sector which is not being program • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface (CFI) HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC input pin - Hardware write protect pin/Provides accelerated program capability - MX29GL320E T/B: Protect Top or Bottom two sectors if WP#/ACC=Vil - MX29GL320E H/L: Protect first or last sector if WP#/ACC=Vil PACKAGE • MX29GL320E T/B - 48-pin TSOP - 48-ball LFBGA (6x8mm) • MX29GL320E H/L - 56-pin TSOP - 64-ball LFBGA (11x13mm)
P/N:PM1509 REV. 1.0, OCT. 12, 2009
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MX29GL320E T/B MX29GL320E H/L
PIN CONFIGURATION for MX29GL320E T/B
48 TSOP
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0
48 LFBGA
A B C D E F G H
6 5 4 3 2 1
A13
A12
A14
A15
A16
BYTE#
Q15/ A-1 Q13
GND
A9
A8 RESET# WP#/ ACC A17
A10
A11
Q7
Q14
Q6
WE# RY/ BY# A7
NC
A19
Q5
Q12
VCC
Q4 6.0 mm
A18
A20
Q2
Q10
Q11
Q3
A6
A5
Q0
Q8
Q9
Q1
A3
A4
A2
A1
A0
CE#
OE#
GND
8.0 mm
P/N:PM1509
REV. 1.0, OCT. 12, 2009
3
MX29GL320E T/B MX29GL320E H/L
PIN CONFIGURATION for MX29GL320E H/L
56 TSOP
NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 NC VI/O
64 LFBGA
8
NC NC NC VIO GND NC NC NC
7 6
A13
A12
A14
A15
A16
BYTE#
Q15/ A-1 Q13
GND
A9
A8
A10
A11
Q7
Q14
Q6
5
WE#
RESET# WP#/ ACC A17
NC
A19
Q5
Q12
VCC
Q4
4
RY/ BY# A7
A18
A20
Q2
Q10
Q11
Q3
3
A6
A5
Q0
Q8
Q9
Q1
2
A3
A4
A2
A1
A0
CE#
OE#
GND
1
NC
NC
NC
NC
NC
VIO
NC
NC
A
B
C
D
E
F
G
H
P/N:PM1509
REV. 1.0, OCT. 12, 2009
4
MX29GL320E T/B MX29GL320E H/L
PIN DESCRIPTION
SYMBOL PIN NAME A0~A20 Q0~Q14 Q15/A-1 CE# WE# OE# RESET# Address Input Data Inputs/Outputs Q15(Word Mode)/LSB addr(Byte Mode) Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low LOGIC SYMBOL
21 A0-A20 Q0-Q15 (A-1)
16 or 8
CE# OE# WE# RESET# WP#/ACC BYTE# VI/O RY/BY#
Hardware Write Protect/Programming WP#/ACC* Acceleration input RY/BY# Read/Busy Output BYTE# Selects 8 bits or 16 bits mode VCC +3.0V single power supply GND Device Ground NC Pin Not Connected Internally VI/O Power Supply for Input/Output Notes: 1. WP#/ACC has internal pull up. 2. VI/O voltage must tight with VCC. VI/O = VCC =2.7V~3.6V.
P/N:PM1509
REV. 1.0, OCT. 12, 2009
5
MX29GL320E T/B MX29GL320E H/L
BLOCK DIAGRAM
CE# OE# WE# RESET# BYTE# WP#/ACC
CONTROL INPUT LOGIC
WRITE PROGRAM/ERASE HIGH VOLTAGE STATE MACHINE (WSM)
STATE FLASH ARRAY ARRAY Y-PASS GATE SOURCE HV COMMAND DATA DECODER REGISTER
X-DECODER
ADDRESS LATCH A0-AM AND BUFFER
SEN.