Document
128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
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AS8C403600 AS8C401800
Features
128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial: – 150MHz 3.8ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control ( GW l ( ), byte write enable (BWE), and byte writes ( BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP).
Description
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TheAS8C403600/1800 are high- speed SRAMs organized as 128K x 36/256K x 18. The AS8C403600/401800 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer,as theAS8C403600/1800 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (A ( DV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The AS8C403600/1800 SRAMs utilize the latest high- performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP).
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input I/O Supply Supply Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Synchronous Synchronous N/A Synchronous Asynchronous Synchronous N/A N/A
Pin Description Summar y
A0-A17 CE CS0, CS1 OE GW BWE BW1, BW2, BW3, BW4 CLK ADV ADSC ADSP LBO TMS TDI TCK TDO ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, V DDQ VSS
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Address In puts Chip Enab le Chip Se lects Output Enable Global Write Enable Byte Write Enable Individual By te Write Se lects Clock Burst Ad dress Advance Address Status (Cache Controller) Address S tatus (Processor) Linear / Interleaved Burst Order Test Mode Select Test Data Input Test Clock Test Data Output Sleep Mode Data Input / Ou tput Core P ower, I/O P ower Ground
NOTE: 1. BW3 and BW4 are not applicable for the AS8C401800.
September 2010
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DSC-5279/05
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Pin Definitions(1)
Symbol A0-A17 ADSC ADSP Pin Function Address Inputs Address Status (Cache Controller) Address Status (Processor) Burst Address Advance Byte Wr ite Enable Individual Byte Write E nables Chip Enable Clock Chip Se lect 0 Chip Se lect 1 Global Write Enable Data Input/Output Linear B urst Order Output E nable Test ModeSelect Test Data Input Test Clock Test Da taOutput Sleep Mode Power S upply Power Supply Ground No Connect I/O I I I I Active N/A LOW LOW LOW Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Lo w o r ADSP Low and CE Lo w. Synchronous Address Status from Cache Controller. ADSC i s an active LOW i nput that i s used to l oad the address registers with new addresses. Synchronous Address Status from Processor. ADSP i s an ac tive LOW i nput that is us ed to l oad the address registers with new addresses. ADSP is gated by CE. Synchronous Address Advance. ADV i s an a ctive L OW i nput that i s u sed to advance the i nternal burst c ounter, controlling burst access after the initial address is loaded. When the i nput is HIGH the burst c ounter i s n ot i ncremented; th at i s, th ere i s n o a ddress a dvance. Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx i nputs a re p assed to the next s tage i n the c ircuit. If BWE is HIGH then the byte write inputs are blocked and only GW c an i nitiate a w rite cycle. Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte write causes all outputs to be disabled. Synchronous c hip enable. CE is used with CS0 and CS1 to e nable the AS8C403600/1800. CE al so g ates ADSP. This i s the clock i nput. A ll ti ming references fo r the d evice a re made with respect to th is i nput. Synchronous active HIGH c hip select. CS 0 is used with CE and CS1 to e nable th e c hip. Synchronous active LOW chip select. CS1 is used with CE and CS0 to e nable the c hip. Synchronous global write enable. This in.