AS8C803601

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs ◆ AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. 256K x 36, 512K x 18 memory configurations ◆ The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronous signal and can be (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles used to disable the outputsat any given time. ◆ Internally synchronized output buffer enable eliminates the A Clock Enable(CEN) pin allows operation of the to AS8C803601/ 801801 be suspended as long as necessary. All synchronous inputs are ignored when need to control OE ◆ (CEN)is high and the internal device registers will hold their previous values. Single R/ W (READ/WRITE) control pin ◆ There are three chip enable pins (CE1, CE2, CE2) that allow the user Positive clock-edge triggered address, data, and control to deselect the device when desired. If any one of these three are not asserted signal registers for fully pipelined applications ◆ when ADV/LD is low, no new memory operation can be initiated. However, 4-word burst capability (interleaved or linear) ◆ Individual byte write ( BW1 - BW4) control (May tie active) any pending data transfers (reads or writes) will be completed. Th...