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AS8C801801 Dataheets PDF



Part Number AS8C801801
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 3.3V Synchronous ZBT SRAMs
Datasheet AS8C801801 DatasheetAS8C801801 Datasheet (PDF)

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs ◆ AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. 256K x 36, 512K x 18 memory configurations ◆ The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronous signal a.

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256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs ◆ AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. 256K x 36, 512K x 18 memory configurations ◆ The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronous signal and can be (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles used to disable the outputsat any given time. ◆ Internally synchronized output buffer enable eliminates the A Clock Enable(CEN) pin allows operation of the to AS8C803601/ 801801 be suspended as long as necessary. All synchronous inputs are ignored when need to control OE ◆ (CEN)is high and the internal device registers will hold their previous values. Single R/ W (READ/WRITE) control pin ◆ There are three chip enable pins (CE1, CE2, CE2) that allow the user Positive clock-edge triggered address, data, and control to deselect the device when desired. If any one of these three are not asserted signal registers for fully pipelined applications ◆ when ADV/LD is low, no new memory operation can be initiated. However, 4-word burst capability (interleaved or linear) ◆ Individual byte write ( BW1 - BW4) control (May tie active) any pending data transfers (reads or writes) will be completed. The data bus ◆ will tri-state two cycles after chip is deselected or a write is initiated. Three chip enables for simple depth expansion ◆ TheAS8C803601/801801 have an on-chip burst counter. In the burst 3.3V power supply (±5%) ◆ mode,the AS8C803601/801801 can provide fourcycles of data for a single 3.3V I/O Supply (V DDQ) ◆ address presented to the SRAM. The order of the burst sequence is Power down controlled by ZZ input ◆ defined by the LBO input pin. The LBO pin selects between linear and Packaged in a JEDEC standard 100-pin plastic thin quad interleaved burst sequence. The ADV/ LD signal is used to load a new flatpack (TQFP). external address (ADV/ LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). Description The AS8C803601/801801 SRAM utilize IDT's latest high-performance The AS8C803601/801801 are3.3V high-speed 9,437,184 bit CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus pin thin plastic quad flatpack (TQFP) . cycles when turning the bus around between reads and writes, or writes and TM reads. Thus, they have been given the name ZBT , or Zero Bus Turnaround. Features Pin Description Summar y A0-A18 CE1, CE2, CE2 OE R/W CEN BW1, BW2, BW3, BW4 CLK ADV/ LD LBO ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, V DDQ VSS Address Inputs Chip Enables Output Enable Read/Write S ignal Clock Enable Individual Byte Write Selects Clock Advance burst address / Load new address Linear / In terleaved B urst Order Sleep Mode Data Input / Output Core P ower, I/ O Power Ground Input Input Input Input Input Input Input Input Input Input I/O Supply Supply Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Static Asynchronous Synchronous Static Static 5304 tbl 01 SEPTEMBER 2010 1 DSC-5304/07 AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Pin Definitions(1) Symbol A 0-A 18 ADV/ LD Pin Function Address Inputs Advance / Load I/O I I Active N/A N/A Description Synchronous Address inputs. The address register is trig gered by a combination of the rising edge of CLK, ADV/LD lo w, CEN low, and true chip e nables. ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD is sampled hig h then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is s ampled high. R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs re main unchanged. The effect of CEN sampled high on the device outp uts is as if the low to hig h clock transition did not occur. For normal operation, CEN must be s ampled low at rising edge of clock. Synchro nous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also.


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